ISP1362EE/01 PHILIPS [NXP Semiconductors], ISP1362EE/01 Datasheet - Page 97

• Manufacturer Part Number: ISP1362EE/01
• Description: Single-chip Universal Serial Bus On-The-Go controller
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Table 70:
9397 750 12337
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Hc PInterruptEnable register: bit allocation
INTL_IRQ_
Interrupt
Enable
R/W
15
7
0
-
-
15.4.5 Hc PInterruptEnable register (R/W: 25H/A5H)
ClkReady
Table 69:
The bits 9:0 in this register are the same as those in the Hc PInterrupt register. The
bits in this register are used together with bit 0 of the HcHardwareConfiguration
register to enable or disable the bits in the Hc PInterrupt register.
At power-on, all the bits in this register are masked with logic 0. This means no
interrupt request output on the interrupt pin INT1 can be generated. When a bit is set
to logic 1, the interrupt for that bit is enabled.
The bit allocation of the register is given in
Code (Hex): 25 — read
Code (Hex): A5 — write
Bit
2
1
0
R/W
14
6
0
-
-
Hc PInterrupt register: bit description
Suspended
Symbol
ISTL_1_
INT
ISTL_0_
INT
SOF_INT
Enable
R/W
HC
13
5
0
-
-
Rev. 03 — 06 January 2004
reserved
Description
0 — no event
1 — The transaction of the last PTD stored on the ISTL1 buffer has
been completed. The microprocessor is required to read data from
the ISTL1 buffer. The HCD must first read the HcBufferStatus
register to check the status of the ISTL1 buffer before reading data
to the microprocessor.
0 — no event
1 — The transaction of the last PTD stored on the ISTL0 buffer has
been completed. The microprocessor is required to read data from
the ISTL0 buffer. The HCD must first read the HcBufferStatus
register to check the status of the ISTL0 buffer before reading data
to the microprocessor.
0 — no event
1 — The HC is in the SOF state and it indicates the start of a new
frame. The HCD must first read the HcBufferStatus register to
check the status of the ISTL buffer before reading data to the
microprocessor. For the microprocessor to perform the DMA
transfer of ISO data from or to the ISTL buffer, the HC must first
initialize the HcDMAConfiguration register.
Interrupt
Enable
OPR
R/W
12
4
0
-
-
Interrupt
Enable
EOT
R/W
11
3
0
-
-
Table
…continued
70.
Interrupt
ISTL_1
Enable
Single-chip USB OTG controller
R/W
10
2
0
-
-
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
OTG_IRQ_
Interrupt
Interrupt
ISTL_0
Enable
Enable
R/W
R/W
9
0
1
0
ISP1362
ATL_IRQ_
Interrupt
Interrupt
Enable
Enable
SOF
R/W
R/W
97 of 150
8
0
0
0