ISP1362EE/01 PHILIPS [NXP Semiconductors], ISP1362EE/01 Datasheet - Page 74

• Manufacturer Part Number: ISP1362EE/01
• Description: Single-chip Universal Serial Bus On-The-Go controller
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Table 41:
9397 750 12337
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcInteruptStatus register: bit allocation
reserved
31
23
15
7
-
-
-
-
-
-
-
-
15.1.4 HcInterruptStatus register (R/W: 03H/83H)
Table 40:
This register (bit allocation:
hardware interrupts. When an event occurs, the HC sets the corresponding bit in this
register. When a bit is set, a hardware interrupt is generated if the interrupt is enabled
in the HcInterruptEnable register (see
(MIE) bit is set. The HCD may clear specific bits in this register by writing logic 1 to
the bit positions to be cleared. The HC, however, does not clear the bit. The HCD may
not set any of these bits.
Code (Hex): 03 — read
Code (Hex): 83 — write
Bit
31 to 18
17 to 16
15 to 1
0
RHSC
R/W
30
22
14
6
0
-
-
-
-
-
-
HcCommandStatus register: bit description
Symbol
-
SOC[1:0]
-
HCR
FNO
R/W
29
21
13
5
0
-
-
-
-
-
-
Rev. 03 — 06 January 2004
Description
reserved
SchedulingOverrunCount: This field is incremented on each
scheduling overrun error. It is initialized to 00B and wraps around
at 11B. It needs to be incremented when a scheduling overrun is
detected even if SchedulingOverrun in HcInterruptStatus has
already been set. This is used by the HCD to monitor any
persistent scheduling problems.
reserved
HostControllerReset: This bit is set by the HCD to initiate a
software reset of the HC. Regardless of the functional state of
the HC, it moves to the USBSuspend state in which most of the
operational registers are reset except those stated otherwise. This
bit is cleared by the HC on completing the reset operation. The
reset operation must be completed within 10 ms. This bit, when
set, should not cause a reset to the Root Hub and no subsequent
reset signaling should be asserted to its downstream ports.
R/W
UE
Table
28
20
12
4
0
-
-
-
-
-
-
reserved
reserved
reserved
41) provides the status of the events that cause
Section
R/W
RD
27
19
11
3
0
-
-
-
-
-
-
15.1.5) and the MasterInterruptEnable
Single-chip USB OTG controller
R/W
SF
26
18
10
2
0
-
-
-
-
-
-
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
reserved
25
17
9
1
-
-
-
-
-
-
-
-
ISP1362
R/W
SO
74 of 150
24
16
8
0
0
-
-
-
-
-
-