ISP1362EE/01 PHILIPS [NXP Semiconductors], ISP1362EE/01 Datasheet - Page 64

• Manufacturer Part Number: ISP1362EE/01
• Description: Single-chip Universal Serial Bus On-The-Go controller
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Table 26:
9397 750 12337
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
OtgInterrupt register: bit allocation
RESUME
OTG_
R/W
15
7
0
-
-
SUSPND
Table 27:
Bit
15 to 11
10
9
8
7
OTG_
R/W
14
6
0
-
-
OtgInterrupt register: bit description
Symbol
-
OTG_TMR_
TIMEOUT
B_SE0_
SRP
A_SRP_
DET
OTG_
RESUME
CONN_C
reserved
RMT_
R/W
13
5
0
-
-
Rev. 03 — 06 January 2004
Description
reserved
This bit is set whenever the OTG timer attains time-out. Writing
logic 1 clears this bit. Writing logic 0 has no effect.
0 — no event
1 — OTG Timer time-out
This bit is set whenever the device detects more than 2 ms of SE0.
Writing logic 1 clears this bit. Writing logic 0 has no effect.
0 — no event
1 — bus has been in SE0 for more than 2 ms
This bit is used to detect the session request event (SRP) from the
remote device. The SRP event can be either V
line pulsing. Bit 9 (A_SEL_SRP) of the OtgControl register
determines which SRP is selected. Writing logic 1 clears this bit.
Writing logic 0 has no effect.
0 — no event
1 — SRP is detected
This bit is used to detect a J to K state change when the device is
in the ‘suspend’ state. Writing logic 1 clears this bit. Writing logic 0
has no effect.
0 — no event
1 — a resume signal (J
‘suspend’ state
B_SESS_
VLD_C
R/W
12
4
0
-
-
A_SESS_
VLD_C
R/W
11
3
0
-
-
K) is detected when the bus is in the
_TIMEOUT
OTG_TMR
B_SESS_
END_C
Single-chip USB OTG controller
R/W
R/W
10
0
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
A_VBUS_
B_SE0_
VLD_C
SRP
R/W
R/W
9
0
1
0
BUS
ISP1362
pulsing or data
ID_REG_C
A_SRP_
DET
R/W
R/W
64 of 150
8
0
0
0