ISP1362EE/01 PHILIPS [NXP Semiconductors], ISP1362EE/01 Datasheet - Page 46
ISP1362EE/01
Manufacturer Part Number
ISP1362EE/01
Description
Single-chip Universal Serial Bus On-The-Go controller
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheet
1.ISP1362EE01.pdf
(150 pages)
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12.6 Features of the interrupt transfer
12.7 Features of the isochronous (ISO) transfer
12.8 Overcurrent protection circuit
ATL buffer is now ready for processing. Once the ATL_Active bit of the HcBufferStatus
register is set, the USB packet is sent out. The active bit in the PTD is cleared once
the PTD is sent. Depending on the outcome of the USB transfer, the 4-bit completion
code is updated.
Table 13:
The ISP1362 has a built-in overcurrent protection circuitry. You can enable or disable
this feature by setting or resetting AnalogOCEnable (bit 10) of the
HcHardwareConfiguration register. If this feature is disabled, it is assumed that there
is an external overcurrent protection circuitry.
N bits [7:5]
0
1
2
3
4
5
6
7
•
•
•
•
•
•
•
An interrupt transaction is sent out periodically, according to the ‘interrupt polling
rate’ as defined in the PTD.
An interrupt transaction causes an interrupt to the CPU only if the transaction is
ACKed or has error conditions, such as STALL or no respond. An ACK condition
occurs if data is received on the IN token or data is sent out on the OUT token.
An interrupt is activated only once every ms as long as there is ACK for different
interrupt transactions in the interrupt transfer buffer.
Each interrupt transfer (PTD) placed in the INTL buffer can automatically hold or
send data for more than 1 ms. This can be done using the parameters in the PTD.
Supports multi-buffering by using the ISTL0 or ISTL1 toggling mechanism.
The CPU can decide (in ms) how fast it can serve the ISP1362. This gives the
CPU the flexibility to decide how much time it takes to read and fill in the ISO data.
The ISTL buffer can be updated on-the-fly by using the direct addressing memory
architecture.
Interrupt polling
StartingFrame N[4:0]
Frame 0 to 31
Frame 0 to 31
Frame 0 to 31
Frame 0 to 31
Frame 0 to 31
Frame 0 to 31
Frame 0 to 31
Frame 0 to 31
Rev. 03 — 06 January 2004
Interrupt polling interval (2
1
2
4
8
16
32
64
128
Single-chip USB OTG controller
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1362
N
) in ms
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