ISP1362EE/01 PHILIPS [NXP Semiconductors], ISP1362EE/01 Datasheet - Page 21
ISP1362EE/01
Manufacturer Part Number
ISP1362EE/01
Description
Single-chip Universal Serial Bus On-The-Go controller
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheet
1.ISP1362EE01.pdf
(150 pages)
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9.4 PIO access to internal control registers
Table 5
decoding should combine with the chip select signal (CS) and the address lines (A1
and A0). The direction of access of I/O ports, however, is controlled by the RD and
WR signals
(see
command port or writes data to the data port (see
Table 5:
The register structure in the ISP1362 is a command-data register pair structure. A
complete register access needs a command phase followed by a data phase. The
command (also named as the index of a register) is used to inform the ISP1362 about
the register that will be accessed at the data phase.
On the 16-bit data bus of a microprocessor, a command occupies the lower byte and
the upper byte is filled with zeros (see
For 32-bit registers, the access cycle is shown in
phase followed by two data phases.
CS
L
L
L
L
When RD is LOW, the microprocessor reads data from the data port of the ISP1362
Fig 10. Microprocessor access to the HC or the DC.
Figure
When A1 = L, microprocessor accesses the HC.
When A1 = H, microprocessor accesses the DC.
shows the I/O port addressing in the ISP1362. The complete I/O port address
A1
L
L
H
H
I/O port addressing
10). When WR is LOW, the microprocessor writes command to the
Rev. 03 — 06 January 2004
A0
L
H
L
H
P bus interface
Access
R/W
W
R/W
W
A1
BUS INTERFACE
Figure
Data bus width
16 bits
16 bits
16 bits
16 bits
0
1
12).
Device bus interface
Host bus interface
Figure
Figure
Single-chip USB OTG controller
004aaa122
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
13. It consists of a command
11).
Description
HC data port
HC command port
DC data port
DC command port
ISP1362
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