ISP1362EE/01 PHILIPS [NXP Semiconductors], ISP1362EE/01 Datasheet - Page 27

• Manufacturer Part Number: ISP1362EE/01
• Description: Single-chip Universal Serial Bus On-The-Go controller
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
9397 750 12337
Product data
9.6.2 Combining the two DMA channels
9.7.1 Interrupt in the HC and the OTG controller
9.7 Interrupts
Remark: Configure the HcDMAConfiguration register only after you have configured
all the other registers. The ISP1362 will assert DREQ1 once the DMA enable bit in
this register is set.
The ISP1362 allows systems with limited DMA channels to use a single DMA channel
(DMA1) for both the HC and the DC. This option can be enabled by writing logic 1 to
the OneDMA bit of the HcHardwareConfiguration register. If this option is enabled,
the polarity of the DC DMA and the HC DMA must be set to DACK active LOW and
DREQ active HIGH.
Various events in the HC, the DC and the OTG controller can be programmed to
generate a hardware interrupt. By default, the interrupt generated by the HC and the
OTG controller is routed out at the INT1 pin and the interrupt generated by the DC is
routed out at the INT2 pin.
There are two levels of interrupts represented by level 1 and level 2 (see
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Hc PInterrupt
HcTransferCounter
HcDMAConfiguration
– Before initiating the DMA transfer, clear AllEOTInterrupt (bit 3). This bit is set
– If DMACounterEnable of the HcDMAConfiguration register is set (that is, the
– Read or write DMA (bit 0)
– Targeted buffer ISTL0, ISTL1, ATL and INTL (bits 1 to 3)
– DMA enable or disable (bit 4)
– Burst length (bits 5 to 6)
– DMA counter enable (bit 7).
when the DMA transfer is complete.
DMA counter is enabled), HcTransferCounter must be set to the number of
bytes to be transferred.
Rev. 03 — 06 January 2004
Single-chip USB OTG controller
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1362
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