ISP1362EE/01 PHILIPS [NXP Semiconductors], ISP1362EE/01 Datasheet - Page 123

• Manufacturer Part Number: ISP1362EE/01
• Description: Single-chip Universal Serial Bus On-The-Go controller
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Table 128: DcErrorCode register: bit allocation
9397 750 12337
Product data
Bit
Symbol
Reset
Access
UNREAD
R
7
0
16.2.7 Acknowledge Set-up (F4H)
16.3.1 Read Endpoint Error Code (R: A0H–AFH)
16.3 General commands
Table 127: DcEndpointStatusImage register: bit description
This command acknowledges to the host that a Set-up packet was received. The
arrival of a Set-up packet disables the Validate Buffer and Clear Buffer commands for
the control IN and OUT endpoints. The microprocessor needs to re-enable these
commands by sending an Acknowledge Set-up command, see
Code (Hex): F4 — acknowledge set-up
Transaction — none (code only)
This command returns the status of the last transaction of the selected endpoint, as
stored in the DcErrorCode register. Each new transaction overwrites the previous
status information. The bit allocation of the DcErrorCode register is shown in
Table
Code (Hex): A0 to AF — read error code (control OUT, control IN, endpoint 1 to 14)
Transaction — read 1 byte (code or data)
Table 129: DcErrorCode register: bit description
DATA01
Bit
3
2
1
0
Bit
7
6
R
6
0
128.
Symbol
OVERWRITE
SETUPT
CPUBUF
-
Symbol
UNREAD
DATA01
reserved
5
-
-
Rev. 03 — 06 January 2004
Description
This bit is set by hardware. Logic 1 indicates that a new Set-up
packet has overwritten the previous set-up information, before it
was acknowledged or before the endpoint was stalled. This bit is
cleared by reading, if writing the set-up data has finished.
Firmware must check this bit before sending an Acknowledge
Set-up command or stalling the endpoint. Upon reading logic 1,
the firmware must stop ongoing set-up actions and wait for a
new Set-up packet.
Logic 1 indicates that the buffer contains a Set-up packet.
This bit indicates which buffer is currently selected for CPU
access (0 = primary buffer; 1 = secondary buffer).
reserved
Description
Logic 1 indicates that a new event occurred before the previous
status was read.
This bit indicates the PID type of the last successfully received
or transmitted packet (0 = DATA0 PID; 1 = DATA1 PID).
R
4
0
R
3
0
ERROR[3:0]
Single-chip USB OTG controller
R
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
…continued
Section
R
1
0
ISP1362
13.3.6.
RTOK
123 of 150
R
0
0