ISP1362EE/01 PHILIPS [NXP Semiconductors], ISP1362EE/01 Datasheet - Page 59

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ISP1362EE/01

Manufacturer Part Number
ISP1362EE/01
Description
Single-chip Universal Serial Bus On-The-Go controller
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheet

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Product data
Fig 27. Suspend and resume timing.
D_SUSPEND/D_WAKEUP
GOSUSP (bit)
USB BUS
13.5.2 Resume conditions
INT2
CS
The DC in the ISP1362 will remain in the suspend state for at least 5 ms, before
responding to external wake-up events, such as global resume, bus traffic, CS active
or LOW pulse on the D_SUSPEND/D_WAKEUP pin.
Figure 27
In
A — indicates the point at which the USB bus goes to the idle state.
B — after detecting the suspend interrupt, set and clear the GOSUSP bit in the Mode
register.
C — indicates resume condition, which can be a resume signal from the host, a LOW
pulse on the D_SUSPEND/D_WAKEUP pin, or a LOW pulse on the CS pin.
D — indicates remote wake-up. The ISP1362 will drive a K-state on the USB bus for
10 ms after the D_SUSPEND/D_WAKEUP pin goes LOW or the CS pin goes LOW.
Wake-up from the suspend state is initiated either by the USB host or by the
application:
The steps of a wake-up sequence are as follows:
Figure
USB host: drives a K-state on the USB bus (global resume)
Application: remote wake-up using a LOW pulse on pin D_SUSPEND/D_WAKEUP
or a LOW pulse on pin CS (if enabled using bit WKUPCS of the
DcHardwareConfiguration register).
A
27:
shows a typical timing diagram for the DC suspend and resume operations.
suspend
interrupt
> 3 ms
Rev. 03 — 06 January 2004
idle state
> 5 ms
1.8 ms to
2.2 ms
B
C
0.5 ms to
3.5 ms
interrupt
resume
Single-chip USB OTG controller
D
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
K-state
10 ms
ISP1362
004aaa483
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