PIC18C658 MICROCHIP [Microchip Technology], PIC18C658 Datasheet - Page 45

• Manufacturer Part Number: PIC18C658
• Description: High-Performance Microcontrollers with CAN Module
• Manufacturer: MICROCHIP [Microchip Technology]

4.4
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21-bits
wide. The low byte is called the PCL register. This reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<15:8>
bits and is not directly readable or writable. Updates to
the PCH register may be performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits and is not directly
readable or writable. Updates to the PCU register may
be performed through the PCLATU register.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the LSb of PCL is fixed to a value of ’0’.
The PC increments by 2 to address sequential instruc-
tions in the program memory.
The CALL,
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
FIGURE 4-3:
 2000 Microchip Technology Inc.
OSC2/CLKOUT
PCL, PCLATH and PCLATU
(RC mode)
OSC1
RCALL,
Q4
PC
Q2
Q3
Q1
CLOCK/INSTRUCTION CYCLE
Q1
GOTO and program branch
Execute INST (PC-2)
Fetch INST (PC)
Q2
PC
Q3
Advanced Information
Q4
Q1
Execute INST (PC)
Fetch INST (PC+2)
Q2
PC+2
The contents of PCLATH and PCLATU will be trans-
ferred to the program counter by an operation that
writes PCL. Similarly, the upper two bytes of the pro-
gram counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is useful
for computed offsets to the PC (See Section 4.8.1).
4.5
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 4-3.
Q3
Q4
Clocking Scheme/Instruction Cycle
Q1
Execute INST (PC+2)
Fetch INST (PC+4)
Q2
PC+4
PIC18CXX8
Q3
Q4
DS30475A-page 45
Internal
phase
clock