PIC18C658 MICROCHIP [Microchip Technology], PIC18C658 Datasheet - Page 179

• Manufacturer Part Number: PIC18C658
• Description: High-Performance Microcontrollers with CAN Module
• Manufacturer: MICROCHIP [Microchip Technology]

16.3.2
Once Synchronous Master mode is selected, reception
is enabled by setting either enable bit SREN (RCSTA
register), or enable bit CREN (RCSTA register). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, only a single word
is received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
TABLE 16-9:
FIGURE 16-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
 2000 Microchip Technology Inc.
Name
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
SPBRG
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Reception.
RC7/RX/DT pin
RC6/TX/CK pin
Note: Timing diagram demonstrates SYNC Master mode with bit SREN = ’1’ and bit BRGH = ’0’.
(interrupt)
CREN bit
Write to
bit SREN
SREN bit
USART SYNCHRONOUS MASTER
RECEPTION
RCIF bit
RXREG
GIE/GIEH PEIE/GIEL
USART Receive Register
Baud Rate Generator Register
Read
PSPIF
PSPIE
PSPIP
SPEN
CSRC
Bit 7
Q2
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
’0’
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
ADIE
ADIP
ADIF
Bit 6
RX9
TX9
bit0
TMR0IE
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit1
Advanced Information
INT0IE
CREN
SYNC
Bit 4
TXIF
TXIE
TXIP
bit2
ADDEN
SSPIE
SSPIP
SSPIF
RBIE
Bit 3
—
bit3
TMR0IF
CCP1IF
CCP1IE
CCP1IP
BRGH
FERR
Bit 2
Steps to follow when setting up a Synchronous Master
Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
Initialize the SPBRG register for the appropriate
baud rate (Section 16.1).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
Ensure bits CREN and SREN are clear.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
bit CREN.
bit4
TMR2IE
TMR2IP
TMR2IF
INT0IF
OERR
TRMT
Bit 1
bit5
TMR1IE
TMR1IP
TMR1IF
RX9D
TX9D
RBIF
Bit 0
bit6
PIC18CXX8
0000 000x
0000 0000
0000 0000
0000 0000
0000 -00x
0000 0000
0000 0010
0000 0000
Value on
POR,
BOR
bit7
DS30475A-page 179
Value on all
Q1 Q2 Q3 Q4
0000 000u
0000 0000
0000 0000
0000 0000
0000 -00x
0000 0000
0000 0010
0000 0000
RESETS
other
’0’