PIC18C658 MICROCHIP [Microchip Technology], PIC18C658 Datasheet - Page 149

• Manufacturer Part Number: PIC18C658
• Description: High-Performance Microcontrollers with CAN Module
• Manufacturer: MICROCHIP [Microchip Technology]

15.4.1.2
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow con-
dition is defined as either bit BF (SSPSTAT register) is
set or bit SSPOV (SSPCON1 register) is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR registers) must be cleared in
software. The SSPSTAT register is used to determine
the status of the byte.
15.4.1.3
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR regis-
FIGURE 15-7: I
FIGURE 15-8: I
 2000 Microchip Technology Inc.
SDA
SCL
SSPIF
BF
CKP
SDA
SCL
SSPIF
BF
SSPOV
S
S
Reception
Transmission
A7 A6 A5 A4 A3 A2 A1
1
A7
2
1
Data in
Sampled
Receiving Address
2
2
3
C SLAVE MODE WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
C SLAVE MODE WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
A6
2
4
A5
Receiving Address
3
5
A4
4
6
7
A3
R/W=0
5
8
A2
6
ACK
9
A1
Advanced Information
7
D7
1
D6
R/W = 1
2
8
Cleared in software
SSPBUF register is read
Receiving Data
D5
3
9
ACK
responds to SSPIF
D4
Bit SSPOV is set because the SSPBUF register is still full.
4
while CPU
SCL held low
D3
5
D2
6
ter. Then pin RC3/SCK/SCL should be enabled by set-
ting bit CKP (SSPCON1 register). The master must
monitor the SCL pin prior to asserting another clock
pulse. The slave devices may be holding off the master
by stretching the clock. The eight data bits are shifted
out on the falling edge of the SCL input. This ensures
that the SDA signal is valid during the SCL high time
(Figure 15-8).
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the
master-receiver is latched on the rising edge of the
ninth SCL input pulse. If the SDA line is high (not ACK),
then the data transfer is complete. When the ACK is
latched by the slave, the slave logic is reset (resets
SSPSTAT register) and the slave monitors for another
occurrence of the START bit. If the SDA line was low
(ACK), the transmit data must be loaded into the SSP-
BUF register, which also loads the SSPSR register. Pin
RC3/SCK/SCL should be enabled by setting bit CKP.
D1
7
D7
1
SSPBUF is written in software
D0
8
ACK
D6
9
Cleared in software
2
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
D7
1
D5
3
D6
2
D4
4
D5
Receiving Data
3
Transmitting Data
D3
D4
4
5
PIC18CXX8
ACK is not sent.
D3
5
D2
6
D2
6
From SSP interrupt
service routine
D1
7
D1
7
D0
DS30475A-page 149
8
D0
8
Not ACK
R/W = 0
Not ACK
9
9
Bus Master
Terminates
Transfer
P
P