PIC18C658 MICROCHIP [Microchip Technology], PIC18C658 Datasheet - Page 167

• Manufacturer Part Number: PIC18C658
• Description: High-Performance Microcontrollers with CAN Module
• Manufacturer: MICROCHIP [Microchip Technology]

16.0
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Com-
munications Interface or SCI). The USART can be con-
figured as a full duplex asynchronous system that can
communicate with peripheral devices, such as CRT ter-
minals and personal computers, or it can be configured
as a half duplex synchronous system that can commu-
nicate with peripheral devices, such as A/D or D/A inte-
grated circuits, Serial EEPROMs, etc.
REGISTER 16-1:
 2000 Microchip Technology Inc.
ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TXSTA REGISTER
CSRC: Clock Source Select bit
Asynchronous mode
Don’t care
Synchronous mode
1 = Master mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
Unimplemented: Read as '0'
BRGH: High Baud Rate Select bit
Asynchronous mode
1 = High speed
0 = Low speed
Synchronous mode
Unused in this mode
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
TX9D: 9th bit of transmit data. Can be Address/Data bit or a parity bit.
bit 7
Legend:
R = Readable bit
- n = Value at POR
R/W-0
CSRC
Note:
SREN/CREN overrides TXEN in SYNC mode.
R/W-0
TX9
Advanced Information
R/W-0
TXEN
W = Writable bit
’1’ = Bit is set
R/W-0
SYNC
The USART can be configured in the following modes:
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
The SPEN (RCSTA register) and the TRISC<7> bits
have to be set, and the TRISC<6> bit must be
cleared, in order to configure pins RC6/TX/CK and
RC7/RX/DT as the Universal Synchronous Asynchro-
nous Receiver Transmitter.
Register 16-1 shows the Transmit Status and Control
Register (TXSTA) and Register 16-2 shows the
Receive Status and Control Register (TXSTA).
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
U-0
—
R/W-0
BRGH
PIC18CXX8
x = Bit is unknown
TRMT
R-1
DS30475A-page 167
R/W-0
TX9D
bit 0