PIC18C658 MICROCHIP [Microchip Technology], PIC18C658 Datasheet - Page 295
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PIC18C658
Manufacturer Part Number
PIC18C658
Description
High-Performance Microcontrollers with CAN Module
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18C658.pdf
(366 pages)
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RRNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example 1:
Example 2:
2000 Microchip Technology Inc.
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
REG
N
Z
REG
N
Z
WREG
REG
N
Z
WREG
REG
N
Z
Q1
=
=
=
=
=
=
=
=
=
=
=
=
=
=
register ’f’
Rotate Right f (no carry)
[ label ]
0
d
a
(f<n>)
(f<0>)
N,Z
The contents of register ’f’ are
rotated one bit to the right. If ’d’ is 0,
the result is placed in WREG. If ’d’
is 1, the result is placed back in
register 'f' (default). If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
1
1
RRNCF
RRNCF
Read
0100
Q2
1101 0111
?
?
1110 1011
1
0
?
1101 0111
?
?
1110 1011
1101 0111
1
0
f
[0,1]
[0,1]
255
dest<n-1>,
dest<7>
REG
REG, 0, 0
RRNCF f [ ,d [,a] ]
00da
Process
Data
Q3
register f
ffff
Advanced Information
destination
Write to
Q4
ffff
SETF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Decode
REG
REG
Q1
register ’f’
Set f
[label] SETF
0
a
FFh
None
The contents of the specified regis-
ter are set to FFh. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
1
1
SETF
Read
0110
Q2
=
=
f
[0,1]
PIC18CXX8
255
f
0x5A
0xFF
100a
Process
Data
f [,a]
Q3
DS30475A-page 295
REG
ffff
register ’f’
Write
Q4
ffff
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