PIC18C658 MICROCHIP [Microchip Technology], PIC18C658 Datasheet - Page 30
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PIC18C658
Manufacturer Part Number
PIC18C658
Description
High-Performance Microcontrollers with CAN Module
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18C658.pdf
(366 pages)
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PIC18CXX8
3.1
A Power-on Reset pulse is generated on-chip when a
V
cuitry, connect the MCLR pin directly (or through a
resistor) to V
nents usually needed to create a Power-on Reset
delay. A minimum rise rate for V
eter D004). For a slow rise time, see Figure 3-2.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the device
must be held in RESET until the operating conditions
are met. Brown-out Reset may be used to meet the
voltage start-up condition.
FIGURE 3-2:
DS30475A-page 30
Note 1: External Power-on Reset circuit is required
DD
rise is detected. To take advantage of the POR cir-
2: R < 40 kΩ is recommended to make sure
3: R1 = 100Ω to 1 kΩ will limit any current
Power-on Reset (POR)
only if the V
The diode D helps discharge the capacitor
quickly when V
that the voltage drop across R does not
violate the device’s electrical specification.
flowing into MCLR from external capacitor
C in the event of MCLR/V
down due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS).
D
DD
. This will eliminate external RC compo-
V
DD
EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
V
R
DD
C
DD
POWER-UP)
power-up slope is too slow.
DD
R1
powers down.
DD
PIC18CXX8
MCLR
is specified (param-
PP
pin break-
Advanced Information
3.2
The Power-up Timer provides a fixed nominal time-out
(parameter #33), only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in RESET as long as the PWRT is
active. The PWRT’s time delay allows V
acceptable level. A configuration bit (PWRTEN in
CONFIG2L register) is provided to enable/disable the
PWRT.
The power-up time delay will vary from chip to chip due
to V
parameter #33 for details.
3.3
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This ensures that
the crystal oscillator or resonator has started and stabi-
lized.
The OST time-out is invoked only for XT, LP, HS and
HS4 modes and only on Power-on Reset or wake-up
from SLEEP.
3.4
With the PLL enabled, the time-out sequence following
a Power-on Reset is different from other oscillator
modes. A portion of the Power-up Timer is used to pro-
vide a fixed time-out that is sufficient for the PLL to lock
to the main oscillator frequency. This PLL lock time-out
(T
start-up time-out (OST).
3.5
A
clear/programmed) or enable (if set) the Brown-out
Reset circuitry. If V
greater than parameter #35, the brown-out situation
resets the chip. A RESET may not occur if V
below parameter D005 for less than parameter #35.
The chip will remain in Brown-out Reset until V
above BV
and will keep the chip in RESET an additional time
delay (parameter #33). If V
the Power-up Timer is running, the chip will go back
into a Brown-out Reset and the Power-up Timer will be
initialized. Once V
Timer will execute the additional time delay.
PLL
configuration
DD
) is typically 2 ms and follows the oscillator
, temperature and process variation. See DC
Power-up Timer (PWRT)
Oscillator Start-up Timer (OST)
PLL Lock Time-out
Brown-out Reset (BOR)
DD
. The Power-up Timer will then be invoked
DD
DD
bit,
rises above BV
falls below parameter D005 for
2000 Microchip Technology Inc.
BOREN,
DD
drops below BV
can
DD
DD
, the Power-up
to rise to an
disable
DD
DD
DD
while
rises
falls
(if
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