PIC18C658 MICROCHIP [Microchip Technology], PIC18C658 Datasheet - Page 283
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PIC18C658
Manufacturer Part Number
PIC18C658
Description
High-Performance Microcontrollers with CAN Module
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18C658.pdf
(366 pages)
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INCFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Example:
2000 Microchip Technology Inc.
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
CNT
If CNT
If CNT
Q1
Q1
Q1
PC =
PC =
=
=
=
register ’f’
operation
operation
operation
Increment f, skip if 0
[ label ]
0
d
a
(f) + 1
skip if result = 0
None
The contents of register ’f’ are
incremented. If ’d’ is 0, the result is
placed in WREG. If ’d’ is 1, the
result is placed back in register ’f’
(default).
If the result is 0, the next instruc-
tion, which is already fetched, is
discarded, and a NOP is executed
instead making it a two-cycle
instruction. If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
1
1(2)
Note: 3 cycles if skip and followed
HERE
NZERO
ZERO
Read
0011
No
No
No
Q2
Q2
Q2
Address (HERE)
CNT + 1
0;
Address(ZERO)
0;
Address(NZERO)
f
[0,1]
[0,1]
by a 2-word instruction.
255
dest,
INCFSZ
:
:
INCFSZ f [ ,d [,a] ]
11da
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
ffff
CNT
Advanced Information
destination
operation
operation
operation
Write to
No
No
No
Q4
Q4
Q4
ffff
INFSNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Example:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
REG
If REG
If REG
No
No
No
Q1
Q1
Q1
PC =
PC =
=
=
=
register ’f’
operation
operation
operation
Increment f, skip if not 0
[label]
0
d
a
(f) + 1
skip if result
None
The contents of register 'f' are
incremented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the
result is placed back in register 'f'
(default).
If the result is not 0, the next
instruction, which is already
fetched, is discarded, and a NOP is
executed instead making it a two-
cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
1
1(2)
Note: 3 cycles if skip and followed
HERE
ZERO
NZERO
Read
0100
No
No
No
Q2
Q2
Q2
Address (HERE)
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
f
[0,1]
[0,1]
PIC18CXX8
by a 2-word instruction.
255
INFSNZ f [, d [,a] ]
dest,
INFSNZ
10da
operation
operation
operation
Process
Data
0
No
No
No
Q3
Q3
Q3
DS30475A-page 283
REG
ffff
destination
operation
operation
operation
Write to
No
No
No
Q4
Q4
Q4
ffff
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