PIC18C658 MICROCHIP [Microchip Technology], PIC18C658 Datasheet - Page 155

• Manufacturer Part Number: PIC18C658
• Description: High-Performance Microcontrollers with CAN Module
• Manufacturer: MICROCHIP [Microchip Technology]

15.4.7
A Repeated START condition occurs when the RSEN
bit (SSPCON2 register) is programmed high and the
I
bit is set, the SCL pin is asserted low. When the SCL
pin is sampled low, the baud rate generator is loaded
with the contents of SSPADD<5:0> and begins count-
ing. The SDA pin is released (brought high) for one
baud rate generator count (T
generator times out, if SDA is sampled high, the SCL
pin will be de-asserted (brought high). When SCL is
sampled high, the baud rate generator is re-loaded with
the contents of SSPADD<6:0> and begins counting.
SDA and SCL must be sampled high for one T
This action is then followed by assertion of the SDA pin
(SDA = 0) for one T
this, the RSEN bit (SSPCON2 register) will be automat-
ically cleared and the baud rate generator will not be
reloaded, leaving the SDA pin held low. As soon as a
START condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT register) will be set. The SSPIF bit
will not be set until the baud rate generator has
timed-out.
FIGURE 15-14: REPEAT START CONDITION WAVEFORM
 2000 Microchip Technology Inc.
2
C logic module is in the IDLE state. When the RSEN
Note 1: If RSEN is programmed while any other
2: A bus collision during the Repeated
I
CONDITION TIMING
2
C MASTER MODE REPEATED START
event is in progress, it will not take effect.
START condition occurs if:
• SDA is sampled low when SCL goes
• SCL goes low before SDA is
from low to high.
asserted low. This may indicate that
another master is attempting to
transmit a data "1".
Falling edge of ninth clock
BRG ,
SDA
SCL
while SCL is high. Following
BRG
End of Xmit
). When the baud rate
Write to SSPCON2
occurs here.
SDA = 1,
SCL(no change)
Advanced Information
BRG
T
SDA = 1,
SCL = 1
.
BRG
T
BRG
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional
eight bits of address (10-bit mode) or eight bits of data
(7-bit mode).
15.4.7.1
If the user writes the SSPBUF when a Repeated
START sequence is in progress, the WCOL is set and
the contents of the buffer are unchanged (the write
doesn’t occur).
Note:
Sr = Repeated START
T
BRG
At completion of START bit,
hardware clear RSEN bit
Set S (SSPSTAT<3>)
WCOL Status Flag
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
START condition is complete.
and set SSPIF
Write to SSPBUF occurs here.
T
BRG
1st Bit
T
BRG
PIC18CXX8
DS30475A-page 155