PIC18C658 MICROCHIP [Microchip Technology], PIC18C658 Datasheet - Page 143

• Manufacturer Part Number: PIC18C658
• Description: High-Performance Microcontrollers with CAN Module
• Manufacturer: MICROCHIP [Microchip Technology]

15.3.3
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave is to broadcast data by the software
protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be dis-
abled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “line activity monitor” mode.
The clock polarity is selected by appropriately program-
ming the CKP bit (SSPCON1 register). This, then,
would give waveforms for SPI communication as
FIGURE 15-2: SPI MODE WAVEFORM (MASTER MODE)
 2000 Microchip Technology Inc.
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
SDO
(CKE = 1)
SDI
(SMP = 0)
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
MASTER MODE
bit7
bit7
bit7
bit7
bit6
bit6
Advanced Information
bit5
bit5
bit4
bit4
shown in Figure 15-2, Figure 15-4, and Figure 15-5,
where the MSb is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user programmable to be one
of the following:
• F
• F
• F
• Timer2 output/2
This allows a maximum data rate (at 40 MHz) of 10.00
Mbps.
Figure 15-2 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
bit3
bit3
OSC
OSC
OSC
/4 (or T
/16 (or 4 • T
/64 (or 16 • T
bit2
bit2
CY
)
CY
bit1
bit1
CY
)
)
PIC18CXX8
bit0
bit0
bit0
bit0
DS30475A-page 143
Next Q4 Cycle
after Q2 ↓
4 Clock
Modes