PIC18C658 MICROCHIP [Microchip Technology], PIC18C658 Datasheet - Page 269

• Manufacturer Part Number: PIC18C658
• Description: High-Performance Microcontrollers with CAN Module
• Manufacturer: MICROCHIP [Microchip Technology]

ANDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
2000 Microchip Technology Inc.
Before Instruction
After Instruction
Decode
WREG
REG
N
Z
WREG
REG
N
Z
Q1
=
=
=
=
=
=
=
=
register ’f’
AND WREG with f
[ label ] ANDWF
0
d
a
(WREG) .AND. (f)
N,Z
The contents of WREG are AND’ed
with register 'f'. If 'd' is 0, the result
is stored in WREG. If 'd' is 1, the
result is stored back in register 'f'
(default). If ’a’ is 0, the Access
Bank will be selected. If ’a’ is 1, the
bank will be selected as per the
BSR value.
1
1
ANDWF
Read
0001
Q2
0x17
0xC2
?
?
0x02
0xC2
0
0
f
[0,1]
[0,1]
255
01da
REG, W
Process
Data
Q3
ffff
f [ ,d [,a] ]
dest
Advanced Information
destination
Write to
Q4
ffff
BC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If Jump:
Example:
If No Jump:
Before Instruction
After Instruction
Q1
operation
Decode
Decode
PC
If Carry
If Carry
No
Q1
PC
PC
Read literal
Q2
Read literal
operation
Branch if Carry
[ label ] BC
-128
if carry bit is ’1’
None
If the Carry bit is ’1’, then the pro-
gram will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
1
1(2)
HERE
(PC) + 2 + 2n
1110
No
Q2
’n’
’n’
=
=
=
=
PIC18CXX8
n
address (HERE)
1;
address (HERE+12)
0;
address (HERE+2)
127
0010
Q3
operation
BC
Process
Process
Data
Data
n
No
Q3
DS30475A-page 269
5
PC
nnnn
Write to PC
Q4
operation
operation
No
No
Q4
nnnn