DAC1408D650HW/C1 NXP [NXP Semiconductors], DAC1408D650HW/C1 Datasheet - Page 84

• Manufacturer Part Number: DAC1408D650HW/C1
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Table 59. MISC_CNTRLS register (address 1Ah)
Table 60. IO_MUX_CNTRL0 register (address 1Bh)
Table 61. IO_MUX_CNTRL1 register (address 1Ch)
Table 62. DIG_VERSION register (address 1Dh)
Table 63. JRX_ANA_VERSION register (address 1Eh)
Table 64. PAGE_ADDRESS register (address 1Fh)
Table 65. Page 4 register allocation map . . . . . . . . . . . .50
Table 66. SR_DLP_0 register (address 00h)
Table 67. SR_DLP_1 register (address 01h)
Table 68. FORCE_LOCK register (address 02h)
Table 69. MAN_LOCK_LN_1_0 register (address 03h)
Table 70. MAN_LOCK_2_0 register (address 04h)
Table 71. CA_CNTRL register (address 05h)
Table 72. SCR-CNTRL register (address 06h)
Table 73. ILA_CNTRL register (address 07h)
Table 74. FORCE_ALIGN register (address 08h)
Table 75. MAN_ALIGN_LN_0_1 register (address 09h)
Table 76. MAN_ALIGN_LN_0_1 register (address 0Ah)
Table 77. FA_ERR_HANDLING register (address 0Bh)
Table 78. SYNCOUT_MODE register (address 0Ch)
Table 79. LANE_POLARITY register (address 1Dh)
Table 80. LANE_SELECT register (address 0Eh)
Table 81. SOFT_RESET_SCRAMBLER register
Table 82. INIT_SCR_S15T8_LN0 register
Table 83. INIT_SCR_S7T1_LN0 (address 12h)
Table 84. INIT_SCR_S15T8_LN1 register
DAC1408D650_1
Objective data sheet
bit description . . . . . . . . . . . . . . . . . . . . . . . . .47
bit description . . . . . . . . . . . . . . . . . . . . . . . . .47
bit description . . . . . . . . . . . . . . . . . . . . . . . . .48
bit description . . . . . . . . . . . . . . . . . . . . . . . . .48
bit description . . . . . . . . . . . . . . . . . . . . . . . . .49
bit description . . . . . . . . . . . . . . . . . . . . . . . . .49
bit description . . . . . . . . . . . . . . . . . . . . . . . . .49
bit description . . . . . . . . . . . . . . . . . . . . . . . . .52
bit description . . . . . . . . . . . . . . . . . . . . . . . . .52
bit description . . . . . . . . . . . . . . . . . . . . . . . . .52
bit description . . . . . . . . . . . . . . . . . . . . . . . . .53
bit description . . . . . . . . . . . . . . . . . . . . . . . . .53
bit description . . . . . . . . . . . . . . . . . . . . . . . . .53
bit description . . . . . . . . . . . . . . . . . . . . . . . . .54
bit description . . . . . . . . . . . . . . . . . . . . . . . . .55
bit description . . . . . . . . . . . . . . . . . . . . . . . . .55
bit description . . . . . . . . . . . . . . . . . . . . . . . . .55
bit description . . . . . . . . . . . . . . . . . . . . . . . . .55
bit description . . . . . . . . . . . . . . . . . . . . . . . . .56
bit description . . . . . . . . . . . . . . . . . . . . . . . . .57
bit description . . . . . . . . . . . . . . . . . . . . . . . . .57
bit description . . . . . . . . . . . . . . . . . . . . . . . . .58
(address 10h) bit description . . . . . . . . . . . . . .58
(address 11h) bit description . . . . . . . . . . . . . .58
bit description . . . . . . . . . . . . . . . . . . . . . . . . .59
Rev. 01 — 26 May 2009
Dual 14-bit DAC, up to 650 Msps, 2 and 4 interpolating
Table 85. INIT_SCR_S7T1_LN1 register (address 14h)
Table 86. INIT_SCR_S15T8_LN2 register (address 15h)
Table 87. INIT_SCR_S7T1_LN2 register (address 16h)
Table 88. INIT_SCR_S15T8_LN3 register (address 17h)
Table 89. INIT_SCR_S7T1_LN3 register (address 18h)
Table 90. INIT_ILA_BUFPTR_LN01 register
Table 91. INIT_ILA_BUFPTR_LN23 register
Table 92. ERROR_HANDLING register (address 1Bh)
Table 93. PAGE_ADDRESS register (address 1Fh)
Table 94. Page 5 register allocation map . . . . . . . . . . . . 61
Table 95. ILA_MON_1_0 register (address 00h)
Table 96. ILA_MON_3_2 register (address 01h)
Table 97. ILA_BUF_ERR register (address 02h)
Table 98. CA_MON register (address 03h)
Table 99. DEC_FLAGS register (address 04h)
Table 100.KOUT_FLAG register (address 05h)
Table 101.K28_LN0_FLAG register (address 06h)
Table 102.K28_LN1_FLAG register (address 07h)
Table 103.K28_LN2_FLAG register (address 08h)
Table 104.K28_LN3_FLAG register (address 09h)
Table 105.LOCK_CNT_MON_LN01 register
Table 106.ILA_MON_3_2 register (address 0Bh)
Table 107.LOCK_CNT_MON_LN23 register
Table 108.FLAG_CNT_LSB_LN0 register
Table 109.FLAG_CNT_MSB_LN0 register
Table 110.FLAG_CNT_LSB_LN1 register
(address 13h) bit description . . . . . . . . . . . . . . 59
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 59
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 59
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 59
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 59
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 59
(address 19h) bit description . . . . . . . . . . . . . . 59
(address 1Ah) bit description . . . . . . . . . . . . . 59
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 60
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 60
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 64
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 64
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 64
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 64
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 64
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65
(address 0Ah) bit description . . . . . . . . . . . . . 65
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65
(address 0Ch) bit description . . . . . . . . . . . . . 65
(address 10h) bit description . . . . . . . . . . . . . . 65
(address 11h) bit description . . . . . . . . . . . . . . 65
DAC1408D650
© NXP B.V. 2009. All rights reserved.
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