DAC1408D650HW/C1 NXP [NXP Semiconductors], DAC1408D650HW/C1 Datasheet - Page 57

• Manufacturer Part Number: DAC1408D650HW/C1
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1408D650_1
Objective data sheet
Table 78.
Default settings are shown highlighted.
Table 79.
Bit
7 to 5
4
3 to 0
Bit
3
2
1
0
Symbol
SEL_RE_INIT[2:0] R/W
SYNC_POL
SEL_SYNC[3:0]
Symbol
POL_LN3L
POL_LN2
POL_LN1
POL_LN0
SYNCOUT_MODE register (address 0Ch) bit description
LANE_POLARITY register (address 1Dh) bit description
Rev. 01 — 26 May 2009
Access Value Description
R/W
R/W
Dual 14-bit DAC, up to 650 Msps, 2 and 4 interpolating
Access Value
R/W
R/W
R/W
R/W
000
001
010
011
100
101
110
111
0
0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
other
i_re_init when 1 of the lane_rst's is active
i_re_init when rst_ln0 or rst_ln1 is active
i_re_init when rst_ln2 or rst_ln3 is active
i_re_init when rst_ln0 is active
i_re_init when rst_ln1 is active
i_re_init when rst_ln2 is active
i_re_init when rst_ln3 is active
i_re_init remains '0'
sync_out is active when low
sync_out is active when high
sync when 1 of the 4 lane_sync's is active
sync when all 4 lane_sync;s are active
sync when sync_ln0 or sync_ln1 is active
sync when both sync_ln0 and sync_ln1 are active
sync when sync_ln2 or sync_ln3 is active
sync when both sync_ln2 and sync_ln3 are active
sync when sync_ln0 is active
sync when sync_ln1 is active
sync when sync_ln2 is active
sync when sync_ln3 is active
sync remains fixed '1'
sync remains fixed '0'
0
1
0
1
0
1
Description
no action
invert all databits of dout_ca_ln3[7:0]
no action
invert all databits of dout_ca_ln2[7:0]
no action
invert all databits of dout_ca_ln1[7:0]
no action
invert all databits of dout_ca_ln0[7:0]
DAC1408D650
© NXP B.V. 2009. All rights reserved.
57 of 88