DAC1408D650HW/C1 NXP [NXP Semiconductors], DAC1408D650HW/C1 Datasheet - Page 18

• Manufacturer Part Number: DAC1408D650HW/C1
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1408D650_1
Objective data sheet
10.2.4 Descrambler
10.2.5 Inter lane alignment
DAC1408D650 supports character replacement whatever the state of the descrambler.
When scrambling isn’t active, the received K28.3 /A/ or K28.7 /F/ will be replaced by the
previous sample. When scrambling is active, the corresponding data octet D28.3 (0xC) or
D28.7 (0xFC) will be used.
The used descrambler is the 16-bit parallel self-synchronous descrambler based on the
polynomial 1+
This feature removes strict PCB design skew compensation between the lanes.
This module handles the alignment of the 4 data streams. Due to interlane-skew and each
PLL per lane concept, these alignment characters may be received at different times by
the receivers. After the sync period, the lock signal will be high. This enables the receiving
of K28.3 /A/ characters.
The /A/-characters provided in the initial alignment sequence are then used to align the 4
data streams. With the bit-field sel_ila (2 bits) (refer to
map”), one can select the used K28.3 /A/ symbol (“00” => use the 1st /A/ symbol, “01” =>
use the 2nd /A/ symbol, “10” => use the 3rd /A/ symbol, “11” => use the 4th /A/ symbol)
during the initial lane alignment. When all receivers have received their first selected /A/,
they start propagating the received data to the frame assembly module at the same point
in time.
This module can compensate up to +7/ 7 frame clock period mis-alignment between the
lanes.
When initial lane alignment isn’t supported the manual alignment mode can be used.
After the initial ila sequence, the lane alignment monitoring starts. When a K28.3 /A/
symbol is received among the user data:
- its position is compared to the value of the alignment monitor counter,
- if 2 successive K28.3 /A/ symbols have been received at a wrong position, a realignment
takes place,
- if the buffers are empty or overflow, this will be indicated by the registers: buff_err_ln0 ..
buff_err_ln3
•
•
•
•
VALID: a code group that is found in the column of the 8b/10b decoding tables
according to the current running disparity.
DISPARITY ERROR: The received code group exists in the 8b/10b decoding table,
but is not found in the proper column according to the current running disparity.
NOT-IN-TABLE ERROR: The received code group is not found in the 8b/10b decoding
table for either disparity.
INVALID: a code group that either shows a disparity error or that does not exist in the
8b/10b decoding table.
14
+
15
. This processing can be turned off.
Rev. 01 — 26 May 2009
Dual 14-bit DAC, up to 650 Msps, 2 and 4 interpolating
Table 65 “Page 4 register allocation
DAC1408D650
© NXP B.V. 2009. All rights reserved.
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