DAC1408D650HW/C1 NXP [NXP Semiconductors], DAC1408D650HW/C1 Datasheet - Page 14

• Manufacturer Part Number: DAC1408D650HW/C1
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
10. Application information
DAC1408D650_1
Objective data sheet
10.1 General description
The DAC1408D650 is a dual 14-bit DAC operating up to 650 Msps. Each DAC consists of
a segmented architecture, comprising a 6-bit thermometer sub-DAC and an 8-bit binary
weighted sub-DAC. With a maximum input data rate of up to 325 Msps and a maximum
output sampling rate of 650 Msps, the DAC1408D650 allows more flexibility for wide
bandwidth and multi-carrier systems. Combined with its quadrature modulator and its
32-bit NCO, the DAC1408D650 simplifies the frequency selection of the system. This is
also possible because of the 2 or 4 interpolation filters that remove undesired images.
DAC1408D650 supports the following JESD204A key features:
DAC1408D650 can be interfaced with any logic devices that features high speed
SERDES functionality. Such macro is now widely available in FPGA from different
vendors. Standalone SERDES ICs can also be used.
To enhance the intrinsic board layout simplification of the JESD204A standard, NXP
includes polarity swapping for each of the lanes and additionally offers lane swapping.
Each physical lane can be configured as being logically lane0 or lane1 or lane2 or lane3.
Each DAC generates two complementary current outputs on pins IOUTAP/IOUTAN and
IOUTBP/IOUTBN. This provides a full-scale output current of up to 20 mA. An internal
reference is available for the reference current which is externally adjustable using pin
VIRES.
The DAC1408D650 must be configured before operating. Therefore, it features an SPI
slave interface to access internal registers. Some of these registers also provide
information about the JESD204A interface status.
The DAC1408D650 operates at both 3.3 V and 1.8 V each of which has separate digital
and analog power supplies. The digital input is 3.3 V compliant and the clock input is
LVDS compliant.
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8b/10b decoding,
Code group synchronization,
Inter-lane alignment,
1+
Character replacement,
TX/RX synchronization management via SYNC signals.
14
+
15
scrambling polynomial,
Rev. 01 — 26 May 2009
Dual 14-bit DAC, up to 650 Msps, 2 and 4 interpolating
DAC1408D650
© NXP B.V. 2009. All rights reserved.
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