DAC1408D650HW/C1 NXP [NXP Semiconductors], DAC1408D650HW/C1 Datasheet - Page 71
DAC1408D650HW/C1
Manufacturer Part Number
DAC1408D650HW/C1
Description
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.DAC1408D650HWC1.pdf
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NXP Semiconductors
DAC1408D650_1
Objective data sheet
10.15.2.10 Page 6 bit definition detailed description
Please refer to
tables, all the values emphasized in bold are the default values.
Table 124. LN0_CFG_0 register (address 00h) bit description
Default settings are shown highlighted.
Table 125. LN0_CFG_1 register (address 01h) bit description
Default settings are shown highlighted.
Table 126. LN0_CFG_2 register (address 02h) bit description
Default settings are shown highlighted.
Table 127. LN0_CFG_3 register (address 03h) bit description
Default settings are shown highlighted.
Table 128. LN0_CFG_4 register (address 04h) bit description
Table 129. LN0_CFG_5 register (address 05h) bit description
Table 130. LN0_CFG_6 register (address 06h) bit description
Table 131. LN0_CFG_7 register (address 07h) bit description
Table 132. LN0_CFG_8 register (address 08h) bit description
Bit
7 to 0 LN0_DID[7:0]
Bit
3 to 0 LN0_BID[3:0]
Bit
4 to 0 LN0_LID[4:0]
Bit
7
4 to 0 LN0_L[4:0]
Bit
7 to 0 LN0_F[7:0]
Bit
4 to 0
Bit
4 to 0
Bit
7 to 6
4 to 0
Bit
4 to 0
Symbol
Symbol
Symbol
Symbol
LN0_SCR
Symbol
Symbol
LN0_K[4:0]
Symbol
LN0_M[7:0]
Symbol
LN0_CS[1:0]
LN0_N[4:0]
Symbol
LN0_N’[4:0]
Table 123
Rev. 01 — 26 May 2009
for a register overview and their default values. In the following
Dual 14-bit DAC, up to 650 Msps, 2 and 4 interpolating
Access Value Description
R/W
Access
R/W
Access
R/W
R/W
Access Value Description
R/W
Access Value Description
R/W
Access Value
R/W
Access Value
R/W
Access Value
R/W
R/W
Access Value
R/W
Value Description
Value Description
Description
Description
Description
Description
DAC1408D650
© NXP B.V. 2009. All rights reserved.
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