DAC1408D650HW/C1 NXP [NXP Semiconductors], DAC1408D650HW/C1 Datasheet - Page 33
![no-image](/images/no-image-200.jpg)
DAC1408D650HW/C1
Manufacturer Part Number
DAC1408D650HW/C1
Description
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.DAC1408D650HWC1.pdf
(88 pages)
- Current page: 33 of 88
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NXP Semiconductors
DAC1408D650_1
Objective data sheet
Figure 20
3.3 V
The constraints to adjust the interface are the output compliance range of the DAC and
the auxiliary DACs, the input common mode level of the AQM, and the range of offset
correction.
Fig 19. An example of a DC interface to a 1.7 V
Fig 20. An example of a DC interface to a 3.3 V
i(cm)
common mode input level.
provides an example of a DC interface with the auxiliary DACs to an AQM with a
IOUTN
IOUTN
IOUTP
IOUTP
AUXP
AUXN
AUXP
AUXN
Rev. 01 — 26 May 2009
IOUTP/IOUTN
V
V
IOUTP/IOUTN
V
V
0 mA to 20 mA
1.1 mA (typ.)
o(cm)
o(dif)(p-p)
o(cm)
o(dif)(p-p)
Dual 14-bit DAC, up to 650 Msps, 2 and 4 interpolating
51.1
54.9
634 k
442 k
= 2.67 V
= 2.75 V
3.3 V
3.3 V
= 1.94 V
= 1.96 V
51.1
54.9
634 k
442 k
442
442
237
237
BBP/BBN
V
V
offset correction up to 36 mV
BBP/BBN
V
V
offset correction up to 36 mV
i(cm)
i(dif)(p-p)
i(cm)
i(dif)(p-p)
i(cm)
i(cm)
= 1.7 V
= 3.3 V
750
698
51.1
= 1.23 V
= 1.5 V
AQM when using auxiliary DACs
5 V
AQM when using auxiliary DACs
750
698
51.1
DAC1408D650
BBP
BBN
BBP
BBN
AQM (V
AQM (V
i(cm)
i(cm)
© NXP B.V. 2009. All rights reserved.
001aaj543
001aaj544
= 1.7 V)
= 3.3 V)
33 of 88
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