DAC1408D650HW/C1 NXP [NXP Semiconductors], DAC1408D650HW/C1 Datasheet - Page 44

• Manufacturer Part Number: DAC1408D650HW/C1
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1408D650_1
Objective data sheet
10.15.2.4 Page 2 bit definition detailed description
Please refer to
tables, all the values emphasized in bold are the default values.
Table 40.
Default settings are shown highlighted.
Table 41.
Default settings are shown highlighted.
Bit
5
4
3
2
1
0
Bit
5
4
3
2
1
0
Symbol
MAN_PON_CLKBUFFER R/W
MAN_PON_ALL
MAN_PON_LN3
MAN_PON_LN2
MAN_PON_LN1]
MAN_PON_LN0
Symbol
FULL_RE_INIT
SYNC_INIT_LEVEL
MAN_PON_CNTRL
MAN_SUPD_CNTRL
FORCE_RESET_DCLK
FORCE_RESET_FCLK
MAINCONTROL register (address 00h) bit description
MAN_PON register (address 01h) bit description
Table 39
Rev. 01 — 26 May 2009
for a register overview and their default values. In the following
Dual 14-bit DAC, up to 650 Msps, 2 and 4 interpolating
Access Value Description
R/W
R/W
R/W
R/W
R/W
R/W
Access Value Description
R/W
R/W
R/W
R/W
R/W
1
0
0
1
1
0
0
1
0
1
0
1
initialization
sync
pon
BangBang PLL
reset_dcl
reset_fclk
pon_clkbuffer (when man_pon_cntrl = 1)
pon_all (when man_pon_cntrl = 1)
pon_ln3 (when man_pon_cntrl = 1)
pon_ln2 (when man_pon_cntrl = 1
pon_ln1 (when man_pon_cntrl = 1)
pon_ln0 (when man_pon_cntrl = 1)
full re-initialization
quick re-initialization
sync starts with '0'
sync starts with '1'
manual control of pon's
pon's jesdrx module controlled by dcsmu
run-in timing BangBang PLL controlled by
dcsmu
manual control of run-in timing BangBang
PLL
release reset_dclk
force reset_dclk
release reset_fclk
force reset_fclk
DAC1408D650
© NXP B.V. 2009. All rights reserved.
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