DAC1408D650HW/C1 NXP [NXP Semiconductors], DAC1408D650HW/C1 Datasheet - Page 52

• Manufacturer Part Number: DAC1408D650HW/C1
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1408D650_1
Objective data sheet
10.15.2.6 Page 4 bit definition detailed description
Please refer to
tables, all the values emphasized in bold are the default values.
Table 66.
Default settings are shown highlighted.
Table 67.
Default settings are shown highlighted.
Table 68.
Default settings are shown highlighted.
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Bit Symbol
7
6
5
4
0
FORCE_LOCK_LN3
FORCE_LOCK_LN22
FORCE_LOCK_LN1
FORCE_LOCK_LN0
SR_ILA
Symbol
SR_CNTRL_LN3
SR_CNTRL_LN2
SR_CNTRL_LN1
SR_CNTRL_LN0
SR_DEC_LN3
SR_DEC_LN2
SR_DEC_LN1
SR_DEC_LN0
Symbol
SR_SWA_LN3
SR_SWA_LN2
SR_SWA_LN1
SR_SWA_LN0
SR_CA_LN3
SR_CA_LN2
SR_CA_LN1
SR_CA_LN0
SR_DLP_0 register (address 00h) bit description
SR_DLP_1 register (address 01h) bit description
FORCE_LOCK register (address 02h) bit description
Table 65
Rev. 01 — 26 May 2009
for a register overview and their default values. In the following
Access Value Description
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Access Value Description
R/W
R/W
R/W
R/W
R/W
Dual 14-bit DAC, up to 650 Msps, 2 and 4 interpolating
Access Value Description
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
1
0
1
0
1
0
1
0
1
1
soft reset controller lane_3
soft reset controller lane_2
soft reset controller lane_1
soft reset controller lane_0
soft reset decoder_10b8b lane_3
soft reset decoder_10b8b lane_2
soft reset decoder_10b8b lane_1
soft reset decoder_10b8b lane_0
soft reset inter-lane-alignment
automatic lock sync_word_alignment lane_3
manual lock sync_word_alignment lane_3
automatic lock sync_word_alignment lane_2
manual lock sync_word_alignment lane_2
automatic lock sync_word_alignment lane_1
manual lock sync_word_alignment lane_1
automatic lock sync_word_alignment lane_0
manual lock sync_word_alignment lane_0
softreset sync_word_alignment lane_3
softreset sync_word_alignment lane_2
softreset sync_word_alignment lane_1
softreset sync_word_alignment lane_0
softreset clock_alignment lane_3
softreset clock_alignment lane_2
softreset clock_alignment lane_1
softreset clock_alignment lane_0
DAC1408D650
© NXP B.V. 2009. All rights reserved.
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