DAC1408D650HW/C1 NXP [NXP Semiconductors], DAC1408D650HW/C1 Datasheet
DAC1408D650HW/C1
Related parts for DAC1408D650HW/C1
DAC1408D650HW/C1 Summary of contents
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DAC1408D650 Dual 14-bit DAC 650 Msps, 2 and 4 interpolating with JESD204A interface Rev. 01 — 26 May 2009 1. General description The DAC1408D650 is a high-speed 14-bit dual channel Digital-to-Analog Converter (DAC) with selectable ...
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... Digital radio links I Instrumentation I Automated Test Equipment (ATE) 4. Ordering information Table 1. Ordering information Type number Package Name DAC1408D650HW/C1 HTQFP100 DAC1408D650_1 Objective data sheet Dual 14-bit DAC 650 Msps, 2 and 4 interpolating Description plastic thermal enhanced thin quad flat package; 100 leads; body ...
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Block diagram SDO SPI CONTROL REGISTERS SYNC_OUTP DIGITAL LAYER PROCESSING SYNC_OUTN VIN_P0 LANE PROC VIN_N0 VIN_P1 LANE PROC VIN_N1 VIN_P2 LANE PROC VIN_N2 VIN_P3 LANE PROC VIN_N3 PLL CLKINP CLKINN CLKP Fig 1. Block diagram SDIO SCS_N SCLK NCO ...
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NXP Semiconductors 6. Pinning information 6.1 Pinning V 1 DDA(3V3) AUXAP 2 AUXAN 3 4 AGND V 5 DDA(1V8 DDA(PLL)(1V8) 7 AGNDPLL 8 CLKP CLKN 9 DGNDPLL DDD(PLL)(1V8) n. DD(IO)(1V8) ...
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NXP Semiconductors 6.2 Pin description Table 2. Symbol V DDA(3V3) AUXAP AUXAN AGND V DDA(1V8) V DDA(PLL)(1V8) AGNDPLL CLKP CLKN DGNDPLL V DDD(PLL)(1V8) n.c. n.c. V DD(IO)(1V8) GNDIO n.c. n.c. V DDD(1V8) DGND n.c. n.c. n.c. n.c. n.c. n.c. AGNDSINTF ...
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NXP Semiconductors Table 2. Symbol VIN_P2 V DDA(SINTF)(1V8) VIN_P3 VIN_N3 AGNDSINTF TRST TMS TCK TDI TDO n.c. n.c. n.c. n.c. V DDD(1V8) DGND n.c. n.c. n.c. n.c. V DD(IO)(1V8) GNDIO SDO SDIO SCLK SCS_N RESET_N n.c. VIRES GAPOUT V DDA(1V8) ...
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NXP Semiconductors Table 2. Symbol V DDA(1V8) AGND V DDA(1V8) AGND IOUTBN IOUTBP AGND n.c. AGND IOUTAP IOUTAN AGND V DDA(1V8) AGND V DDA(1V8) AGND V DDA(1V8) AGND V DDA(1V8) AGND AGND [1] P: power supply; G: ground; I: input; ...
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NXP Semiconductors 7. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V input/output supply voltage DD(IO) V analog supply voltage (3.3 V) DDA(3V3) V analog supply voltage (1.8 V) DDA(1V8) ...
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NXP Semiconductors 9. Characteristics Table 5. Characteristics DDA(1V8) DD(PLL) DDD DD(IO) GNDIO are shorted together; T amb DD(sintf) DDA(3V3) specified. Symbol Parameter V input/output ...
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NXP Semiconductors Table 5. Characteristics …continued DDA(1V8) DD(PLL) DDD DD(IO) GNDIO are shorted together; T amb DD(sintf) DDA(3V3) specified. Symbol Parameter P total power ...
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NXP Semiconductors Table 5. Characteristics …continued DDA(1V8) DD(PLL) DDD DD(IO) GNDIO are shorted together; T amb DD(sintf) DDA(3V3) specified. Symbol Parameter Z V source ...
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NXP Semiconductors Table 5. Characteristics …continued DDA(1V8) DD(PLL) DDD DD(IO) GNDIO are shorted together; T amb DD(sintf) DDA(3V3) specified. Symbol Parameter NCO frequency range; ...
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NXP Semiconductors Table 5. Characteristics …continued DDA(1V8) DD(PLL) DDD DD(IO) GNDIO are shorted together; T amb DD(sintf) DDA(3V3) specified. Symbol Parameter NSD noise spectral ...
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NXP Semiconductors 10. Application information 10.1 General description The DAC1408D650 is a dual 14-bit DAC operating up to 650 Msps. Each DAC consists of a segmented architecture, comprising a 6-bit thermometer sub-DAC and an 8-bit binary weighted sub-DAC. With a ...
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NXP Semiconductors 10.2 JESD204A receiver SYNC_OUT 10b CLOCK lane# DES ALIGN frame clock The descrambler can be enabled/disabled Fig 3. JESD204A receiver The JEDEC204A defines the following parameters: The DAC1408D650 supports both LMF = 421 and LMF = 211. The ...
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NXP Semiconductors Fig 4. The common mode voltage is programmable. See map” for register value. DC coupling is only possible if both DAC and transmitter have the same common mode voltage. Else, AC coupling is required Zdiff = ...
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NXP Semiconductors The SYNC signal is also used during normal operation by the DAC1408D650 to request a link re-initialization. This occurs when the 8b/10b module loses synchronization. The SYNC_OUT signal conforms to LVDS signaling. Its common mode voltage (see 39 ...
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NXP Semiconductors • VALID: a code group that is found in the column of the 8b/10b decoding tables according to the current running disparity. • DISPARITY ERROR: The received code group exists in the 8b/10b decoding table, but is not ...
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NXP Semiconductors 10.2.6 Frame assembly DAC1408D650 supports only / which means that every frame clock period carries one byte per lane. Frame assembly combines the octet of lane_0 with the 6 msb bits of lane_1 and re-assemble the ...
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NXP Semiconductors SERIAL CLOCK 3.125 GHz Fig 8. ...
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NXP Semiconductors This interface can be configured as a 3-wire type (SDIO as bidirectional pin 4-wire type (SDIO and SDO as unidirectional pin, input and output port respectively). In both configurations, SCLK acts as the serial clock, and ...
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NXP Semiconductors RESET_N (optional) SCS_N Fig 10. SPI timing diagram The SPI timing characteristics are given in Table 10. Symbol f SCLK t w(SCLK) t su(SCS_N) t h(SCS_N) t su(SDIO) t h(SDIO) t w(RESET_N) DAC1408D650_1 Objective data sheet Dual 14-bit ...
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NXP Semiconductors 10.4 Clock inputs DAC1408D650 has two differential clock inputs, namely CLKINN/CLKINP and CLKN/CLKP. They must be driven with signals of exactly the same frequency. As the part has internal clock domain transition circuitry, there is no phase requirement ...
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NXP Semiconductors 10.5 FIR Filters The two interpolation FIR filters have a stop band attenuation of at least 80 dBc and a pass band ripple of less than 0,0005 dB. Table 11. First interpolation filter Lower H(1) H(2) H(3) H(4) ...
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NXP Semiconductors 10.6 Quadrature modulator and Numerically Controlled Oscillator (NCO) The quadrature modulator allows the 14-bit I and Q data to be mixed with the carrier signal generated by the NCO. The frequency of the NCO is programmed over 32-bit ...
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NXP Semiconductors Table 12. First interpolation filter Lower H(1) H(2) H(3) H(4) H(5) 10.8 DAC transfer function The full-scale output current for each DAC is the sum of the two complementary current outputs The output current ...
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NXP Semiconductors 10.9 Full-scale current 10.9.1 Regulation Figure 13 integrates an internal bandgap reference voltage which delivers a 1.25 V reference to the GAPOUT pin recommended to decouple pin GAPOUT using a 100 nF capacitor. The reference current ...
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NXP Semiconductors Table 14. Default settings are shown highlighted. DAC_GAIN_COARSE[3:0] Decimal The settings applied to DAC_A_GAIN_FINE[5:0] (register 0Ah; see “DAC_A_CFG_2 register (address 0Ah) bit ...
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NXP Semiconductors (register 0Ch; see register 0Eh; see the range of variation of the digital offset (see Table 16. Default settings are shown highlighted. DAC_OFFSET[11:0] Decimal 2048 2047 ... ... 2046 2047 10.11 Analog output The DAC1408D650 ...
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NXP Semiconductors 10.12 Auxiliary DACs The DAC1408D650 integrates 2 auxiliary DACs that can be used to compensate for any offset between the DAC and the next stage in the transmission path. Both auxiliary DACs have a resolution of 10-bit and ...
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NXP Semiconductors 10.13 Output configuration 10.13.1 Basic output configuration The use of a differentially-coupled transformer output provides optimum distortion performance (see helps to match the impedance and provides electrical isolation. Fig 15 The DAC1408D650 can operate up to ...
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NXP Semiconductors 10.13.2 DC interface to an Analog Quadrature Modulator (AQM) When the system operation requires to keep the DC component of the spectrum, the DAC1408D650 can use a DC interface to connect to an AQM. In this case, the ...
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NXP Semiconductors Fig 19. An example interface to a 1.7 V Figure 20 3.3 V i(cm) Fig 20. An example interface to a 3.3 V The constraints to adjust the interface are the output ...
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NXP Semiconductors 10.13.3 AC interface to an Analog Quadrature Modulator (AQM) When the AQM common mode voltage is close to ground, the DAC1408D650 must be AC-coupled and the auxiliary DACs are needed for offset correction. Figure 20 input level when ...
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NXP Semiconductors 10.15 Configuration interface 10.15.1 Register description DAC1408D650 implements indirect addressing using a page access method. The page-address is located at address 0x1F and is by default 0x00, which selects page_0 as default-page. For example, to access registers which ...
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Page 0 allocation map description Table 18. Page 0 register allocation map Address Register name R/W Bit definition b7 0 00h COMMON R/W SPI_3W 1 01h TXCFG R/W NCO_EN 2 02h PLLCFG R/W PD_PLL 3 03h FREQNCO_LSB R/W 4 ...
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NXP Semiconductors 10.15.2.2 Page 0 bit definition detailed description Please refer to values emphasized in bold are the default values. Table 19. Default settings are shown highlighted. Bit DAC1408D650_1 Objective data sheet Dual 14-bit ...
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NXP Semiconductors Table 20. Default settings are shown highlighted. Bit MODE[2: INT_FIR[1:0] DAC1408D650_1 Objective data sheet Dual 14-bit DAC 650 Msps, 2 and 4 interpolating TXCFG register (address 01h) ...
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NXP Semiconductors Table 21. Default settings are shown highlighted. Bit PLL_DIV[1: PLL_PHASE[1:0] 0 Table 22. Bit FREQ_NCO[7:0] Table 23. Bit FREQ_NCO[15:8] Table 24. Bit 7 ...
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NXP Semiconductors Table 27. Bit PH_NCO[15:8] Table 28. Default settings are shown highlighted. Bit DAC_A_OFFSET[5:0] Table 29. Bit DAC_A_GAIN_COARSE[7:6] R DAC_A_GAIN_FINE[5:0] Table 30. Bit 7 to ...
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NXP Semiconductors Table 33. Bit DAC_B_GAIN_COARSE[9:8] R DAC_B_OFFSET[11:6] Table 34. Default settings are shown highlighted. Bit 1 0 Table 35. Bit Table 36. Default settings are shown highlighted. Bit 7 1 ...
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Page 2 allocation map description Table 39. Page 2 register allocation map Address Register name R/W Bit definition 00h MAINCONTROL R 01h MAN_PON R 02h MAN_SUPD R/W MAN_PLL MAN_PLL _SEL_PD ...
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Table 39. Page 2 register allocation map …continued Address Register name R/W Bit definition 1Dh DIG_VERSION R DIG_VERSION_ID[7:0] 30 1Eh JRX_ANA_VERSI R JRX_ANA_VERSION_ID[7: 1Fh PAGE_ADDRESS R/W PAGE Default b1 b0 Bin ...
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NXP Semiconductors 10.15.2.4 Page 2 bit definition detailed description Please refer to tables, all the values emphasized in bold are the default values. Table 40. Default settings are shown highlighted. Bit Table 41. Default ...
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NXP Semiconductors Table 42. Default settings are shown highlighted. Bit Table 43. Bit RST_EXT_FCLK[7:0] Table 44. Bit RST_EXT_DCLK[7:0] R/W Table 45. Bit DCSMU_PREDIVCNT[7:0] ...
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NXP Semiconductors Table 49. Default settings are shown highlighted. Bit ILEV_CNTRL[1: QLEV_CNTRL[1: IQ_DC_LEVEL[11:9] Table 50. Bit IQ_DC_LEVEL[7:0] Table 51. Bit SET_ICHP_PD1[3:0] Table 52. Default settings ...
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NXP Semiconductors Table 56. Bit Table 57. Default settings are shown highlighted. Bit 7 Table 58. Default settings are shown highlighted. Bit Table 59. Bit ...
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NXP Semiconductors Table 60. Default settings are shown highlighted. Bit Table 61. Bit DAC1408D650_1 Objective data sheet Dual 14-bit DAC 650 Msps, 2 ...
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NXP Semiconductors Table 62. Bit Table 63. Bit Table 64. Bit DAC1408D650_1 Objective data sheet Dual 14-bit DAC 650 Msps, 2 and 4 interpolating DIG_VERSION register (address 1Dh) bit ...
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Page 4 allocation map description Table 65. Page 4 register allocation map Address Register name R/W Bit definition 00h SR_DLP_0 R/W SR_SWA_ SR_SWA_ LN3 1 01h SR_DLP_1 R/W SR_CNTRL SR_CNTRL _LN3 2 02h FORCE_LOCK R/W FORCE_ ...
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Table 65. Page 4 register allocation map …continued Address Register name R/W Bit definition 12h INIT_SCR_ R/W - S7T1_LN0 19 13h INIT_SCR_ R/W S15T8_LN1 20 14h INIT_SCR_ R/W - S7T1_LN1 21 15h INIT_SCR_ R/W S15T8_LN2 22 16h ...
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NXP Semiconductors 10.15.2.6 Page 4 bit definition detailed description Please refer to tables, all the values emphasized in bold are the default values. Table 66. Default settings are shown highlighted. Bit Table ...
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NXP Semiconductors Table 69. Default settings are shown highlighted. Bit MAN_LOCK_LN1[3:0] R MAN_LOCK_LN0[3:0] R/W Table 70. Bit MAN_LOCK_LN3[3:0] R MAN_LOCK_LN2[3:0] R/W Table 71. Bit Symbol 7 WORD_SWAP_LN3 6 ...
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NXP Semiconductors Table 72. Bit Symbol 7 MAN_SCR_LN3 6 MAN_SCR_LN2 5 MAN_SCR_LN1 4 MAN_SCR_LN0 3 FORCE_SRC_LN3 R/W 2 FORCE_SRC_LN2 R/W 1 FORCE_SRC_LN1 R/W 0 FORCE_SRC_LN0 R/W DAC1408D650_1 Objective data sheet Dual 14-bit DAC 650 Msps, 2 and 4 ...
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NXP Semiconductors Table 73. Bit SEL_ILA[1: SEL_LOCK[2: Table 74. Bit Symbol 1 DYN_ALIGN_ENA 0 FORCE_ALIGN Table 75. Bit MAN_ALIGN_LN1[3:0] R MAN_ALIGN_LN0[3:0] R/W Table 76. Bit ...
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NXP Semiconductors Table 77. Default settings are shown highlighted. Bit SEL_KOUT_ SEL_KOUT_ SEL_NIT_ERR_ SEL_NIT_ERR_ DAC1408D650_1 Objective data sheet Dual 14-bit DAC 650 Msps, 2 and 4 ...
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NXP Semiconductors Table 78. Default settings are shown highlighted. Bit Table 79. Bit DAC1408D650_1 Objective data sheet Dual 14-bit DAC 650 Msps, 2 and 4 interpolating SYNCOUT_MODE ...
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NXP Semiconductors Table 80. Default settings are shown highlighted. Bit LANE_SEL_LN3[1: LANE_SEL_LN2[1: LANE_SEL_LN1[1: LANE_SEL_LN0[1:0] Table 81. Bit Table 82. Bit INIT_VALUE_S15_S8_LN0[7:0] ...
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NXP Semiconductors Table 83. Bit INIT_VALUE_S7_S1_LN0[6:0] R/W Table 84. Default settings are shown highlighted. Bit INIT_VALUE_S15_S8_LN1[7:0] R/W Table 85. Bit INIT_VALUE_S7_S1_LN1[6:0] Table 86. Bit INIT_VALUE_S15_S8_LN2[7:0] R/W Table 87. ...
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NXP Semiconductors Table 92. Default settings are shown highlighted. Bit CORR_MODE[1:0] R Table 93. Bit DAC1408D650_1 Objective data sheet Dual 14-bit DAC 650 Msps, 2 and 4 ...
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Page 5 allocation map description Table 94. Page 5 register allocation map Address Register name R/W Bit definition 00h ILA_MON_1_0 R 1 01h ILA_MON_3_2 R 2 02h ILA_BUF_ERR 03h CA_MON R CA_MON_LN3[1:0] 4 ...
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Table 94. Page 5 register allocation map …continued Address Register name R/W Bit definition 16h FLAG_CNT_LSB_ R LN3 23 17h FLAG_CNT_MSB_ R LN3 25 19h BER_LEVEL R/W 26 1Ah INTR_ENA R/W INTR_EN INTR_EN A_NIT A_DISP 27 1Bh ...
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NXP Semiconductors 10.15.2.8 Page 5 bit definition detailed description Please refer to tables, all the values emphasized in bold are the default values. Table 95. Default settings are shown highlighted. Bit ILA_MON_LN1[3: ILA_MON_LN0[3:0] Table ...
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NXP Semiconductors Table 99. Bit Table 100. KOUT_FLAG register (address 05h) bit description Bit Table 101. K28_LN0_FLAG register (address 06h) bit description Bit ...
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NXP Semiconductors Table 104. K28_LN3_FLAG register (address 09h) bit description Bit Table 105. LOCK_CNT_MON_LN01 register (address 0Ah) bit description Bit Table 106. ILA_MON_3_2 register (address 0Bh) bit description Default settings are ...
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NXP Semiconductors Table 112. FLAG_CNT_LSB_LN2 register (address 14h) bit description Default settings are shown highlighted. Bit FLAG_CNT_LN2[7:0] Table 113. FLAG_CNT_MSB_LN2 register (address 15h) bit description Default settings are shown highlighted. Bit FLAG_CNT_LN2[15:8] Table 114. ...
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NXP Semiconductors Table 117. INTR_ENA register (address 1Ah) bit description Bit Symbol 2 INTR_ENA_K28_5 1 INTR_ENA_K28_3 0 INTR_ENA_K28_0 Table 118. CNTRL_FLAGCNT_LN01 register (address 1Bh) bit description Default settings are shown highlighted. Bit SEL_CFC_LN1[2:0] R ...
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NXP Semiconductors Table 121. DBG_CNTRL register (address 1Eh) bit description Bit Table 122. PAGE_ADDRESS register (address 1Fh) bit description Bit DAC1408D650_1 Objective data sheet Dual 14-bit DAC ...
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Page 6 allocation map description Table 123. Page 6 register allocation map Address Register name R/W Bit definition b7 0 00h LN0_CFG_0 R 1 01h LN0_CFG_1 02h LN0_CFG_2 03h LN0_CFG_3 R LN0_SCR 4 ...
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Table 123. Page 6 register allocation map …continued Address Register name R/W Bit definition b7 28 1Ch LN1_CFG_12 R 29 1Dh LN1_CFG_13 R 31 1Fh PAGE_ADDRESS R LN1_RES2[7:0] LN1_FCHK[7:0] PAGE Default Bin Hex ...
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NXP Semiconductors 10.15.2.10 Page 6 bit definition detailed description Please refer to tables, all the values emphasized in bold are the default values. Table 124. LN0_CFG_0 register (address 00h) bit description Default settings are shown highlighted. Bit ...
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NXP Semiconductors Table 133. LN0_CFG_9 register (address 09h) bit description Bit Table 134. LN0_CFG_10 register (address 0Ah) bit description Bit Table 135. LN0_CFG_11 register (address 0Bh) bit description Bit Table ...
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NXP Semiconductors Table 144. LN1_CFG_6 register (address 16h) bit description Bit Table 145. LN1_CFG_7 register (address 17h) bit description Bit Table 146. LN1_CFG_8 register (address 18h) bit description Bit 4 to ...
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Page 7 allocation map description Table 153. Page 7 register allocation map Address Register name R/W Bit definition b7 0 00h LN2_CFG_0 R 1 01h LN2_CFG_1 02h LN2_CFG_2 03h LN2_CFG_3 R LN2_SCR 4 ...
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Table 153. Page 7 register allocation map …continued Address Register name R/W Bit definition b7 28 1Ch LN3_CFG_12 R 29 1Dh LN3_CFG_13 R 31 1Fh PAGE_ADDRESS R LN3_RES2[7:0] LN3_FCHK[7:0] PAGE Default Bin Hex ...
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NXP Semiconductors 10.15.2.12 Page 7 bit definition detailed description Please refer to tables, all the values emphasized in bold are the default values. Table 154. LN2_CFG_0 register (address 00h) bit description Default settings are shown highlighted. Bit ...
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NXP Semiconductors Table 163. LN2_CFG_9 register (address 09h) bit description Bit Table 164. LN2_CFG_10 register (address 0Ah) bit description Bit Table 165. LN2_CFG_11 register (address 0Bh) bit description Bit Table ...
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NXP Semiconductors Table 174. LN3_CFG_6 register (address 16h) bit description Bit Table 175. LN3_CFG_7 register (address 17h) bit description Bit Table 176. LN3_CFG_8 register (address 18h) bit description Bit 4 to ...
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NXP Semiconductors 11. Package outline HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads; body mm; exposed die pad y exposed die pad side pin 1 index 100 ...
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NXP Semiconductors 12. Abbreviations Table 183. Abbreviations Acronym BW BWA CDMA CML CMOS DAC EDGE FIR GSM IF IMD3 LMDS LVDS NCO NMOS PLL SERDES SFDR SPI WCDMA WLL DAC1408D650_1 Objective data sheet Dual 14-bit DAC 650 Msps, ...
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NXP Semiconductors 13. Revision history Table 184. Revision history Document ID Release date DAC1408D650_1 20090526 DAC1408D650_1 Objective data sheet Dual 14-bit DAC 650 Msps, 2 and 4 interpolating Data sheet status Change notice Objective data sheet - Rev. ...
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NXP Semiconductors 14. Legal information 14.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors 16. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Table 2. Pin description . . . . . . . ...
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NXP Semiconductors bit description . . . . . . . . . . . . . . . . . . . . . . . . .47 Table 59. MISC_CNTRLS register (address 1Ah) bit description . . . ...
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NXP Semiconductors (address 12h) bit description . . . . . . . . . . . . . .65 Table 111.FLAG_CNT_MSB_LN1 register (address 13h) bit description . . . . . . . . . . . . . ...
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NXP Semiconductors bit description . . . . . . . . . . . . . . . . . . . . . . . . .76 Table 163.LN2_CFG_9 register (address 09h) bit description . . . . ...
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NXP Semiconductors 17. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Fig 2. Pin configuration ...
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NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...