DAC1408D650HW/C1 NXP [NXP Semiconductors], DAC1408D650HW/C1 Datasheet - Page 46

• Manufacturer Part Number: DAC1408D650HW/C1
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1408D650_1
Objective data sheet
Table 49.
Default settings are shown highlighted.
Table 50.
Table 51.
Table 52.
Default settings are shown highlighted.
Table 53.
Table 54.
Table 55.
Default settings are shown highlighted.
Bit
7 to 6 ILEV_CNTRL[1:0]
5 to 4 QLEV_CNTRL[1:0]
3 to 0 IQ_DC_LEVEL[11:9]
Bit
7 to 0 IQ_DC_LEVEL[7:0]
Bit
3 to 0 SET_ICHP_PD1[3:0]
Bit
3 to 0 SET_ICHP_PD2[3:0]
Bit
3 to 0 SET_ICHP_PFD[3:0]
Bit
3 to 0 SET_RATIO_PD1[3:0]
Bit
3 to 0 SET_RATIO_PD2[3:0]
Symbol
Symbol
Symbol
Symbol
Symbol
Symbol
Symbol
IQ_LEVEL_CNTRL register (address 0Ah) bit description
IQ_DC_LEVEL_LSB register (address 0Bh) bit description
SET_ICHP_PD1 register (address 10h) bit description
SET_ICHP_PD2 register (address 11h) bit description
SET_ICHP_PFD register (address 12h) bit description
SET_RATIO_PD1 register (address 13h) bit description
SET_RATIO_PD2 (address 14h) bit description
Rev. 01 — 26 May 2009
Dual 14-bit DAC, up to 650 Msps, 2 and 4 interpolating
Access Value Description
R/W
R/W
R/W
Access Value
R/W
Access Value Description
R/W
Access Value
R/W
Access Value Description
R/W
Access Value Description
R/W
Access Value Description
R/W
0
1
0
1
-
-
-
01h
-
-
-
I_IN <= DATA_I_CDI
I_IN <= DATA_I_CDI when
EN_DATA_I_CDI='1' else
1X: I_IN <= IQ_DC_LEVEL x 4
Q_IN <= DATA_Q_CDI
Q_IN <= DATA_Q_CDI when
EN_DATA_Q_CDI='1' else
1X: Q_IN <= IQ_DC_LEVEL X 4
msb's iq dc level
Description
proportional charge pump pd ( 45 deg. <
error < 90 deg.)
lsb's iq dc level
integrating charge pump pd ( 45 deg.
error < 90 deg.)
integrating charge pump pfd ( linear PLL)
proportional charge pump pd ( error < 45
deg.)
Description
integrating charge pump pd ( error
deg.)
DAC1408D650
© NXP B.V. 2009. All rights reserved.
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