DAC1408D650HW/C1 NXP [NXP Semiconductors], DAC1408D650HW/C1 Datasheet - Page 11
![no-image](/images/no-image-200.jpg)
DAC1408D650HW/C1
Manufacturer Part Number
DAC1408D650HW/C1
Description
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.DAC1408D650HWC1.pdf
(88 pages)
- Current page: 11 of 88
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NXP Semiconductors
Table 5.
V
GNDIO are shorted together; T
V
specified.
DAC1408D650_1
Objective data sheet
Symbol
Z
Digital outputs (SYNC_OUTN/SYNC_OUTP)
V
V
Analog outputs (IOUTAP, IOUTAN, IOUTBP, IOUTBN)
I
V
R
C
N
Reference voltage output (GAPOUT)
V
I
Analog Auxiliary outputs (AUXAP, AUXAN, AUXBP and AUXBN)
I
V
N
Input timing (Vin_p / Vin_n)
f
f
Output timing (IOUTAP, IOUTAN, IOUTBP, IOUTBN)
f
t
O(fs)
O(ref)
O(aux)
data
bit
s
s
DDA(1V8)
DD(sintf)
tt
Z
E
E
V
o(cm)
o(dif)(p-p)
O
O(ref)
O(aux)
o
o
DAC(mono)
DAC(aux)mono
i
O
G
O(ref)
= 1.8 V; V
= V
Characteristics
DD(PLL)
Parameter
V
differential input
impedance
common-mode output
voltage
peak-to-peak
differential output
voltage
full-scale output
current
output voltage
output resistance
output capacitance
DAC monotonicity
offset error variation
gain error variation
reference output
voltage
reference output
current
reference output
voltage variation
auxiliary output current differential outputs
auxiliary output
voltage
auxiliary DAC
monotonicity
data rate
bit rate
sampling frequency
settling time
tt
DDA(3V3)
source impedance
= V
DDD
= 3.3 V; T
= V
…continued
DD(IO)
amb
= 40 C to +85 C; typical values measured at V
amb
= VDD
= +25 C; R
Conditions
reg value = 00h
reg = default value
compliance range
guaranteed
external voltage 1.2 V
compliance range
guaranteed
4 interpolation
serial input
up to 0.5 LSB
(sintf)
interpolation
[3]
= 1.65 V to 1.95 V; V
Rev. 01 — 26 May 2009
L
= 50 ; I
Dual 14-bit DAC, up to 650 Msps, 2 and 4 interpolating
O(fs)
= 20 mA; maximum sample rate; unless otherwise
DDA(3V3)
Test
C
C
D
C
D
D
D
C
C
I
C
C
I
C
D
C
D
[1]
= 3.0 V to 3.6 V; AGND, GND(PLL), DGND and
DDA(1V8)
Min
-
-
0.79
0.12
-
-
1.8
-
-
-
-
-
tbd
-
-
-
0
-
tbd
tbd
tbd
-
-
DAC1408D650
= V
Typ
0.7
100
0.98
0.48
1.6
20
-
250
3
tbd
tbd
tbd
1.25
39
131
2.2
-
10
-
-
-
-
20
DD(PLL)
= V
Max
-
-
1.46
0.96
-
-
V
-
-
-
-
-
tbd
-
-
-
2
-
325
162.5
3.25
650
-
© NXP B.V. 2009. All rights reserved.
DDA(3V3)
DDD
= V
DD(IO)
Unit
V
V
mA
mA
V
k
pF
bits
ppm/ C
ppm/ C
V
ppm/ C
mA
V
bits
Msps
Msps
Gbps
Msps
ns
A
11 of 88
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