DAC1408D650HW/C1 NXP [NXP Semiconductors], DAC1408D650HW/C1 Datasheet - Page 23

• Manufacturer Part Number: DAC1408D650HW/C1
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1408D650_1
Objective data sheet
10.4 Clock inputs
DAC1408D650 has two differential clock inputs, namely CLKINN/CLKINP and
CLKN/CLKP. They must be driven with signals of exactly the same frequency. As the part
has internal clock domain transition circuitry, there is no phase requirement between the
two clocks.
The DAC1408D650 can operate with a clock frequency up to 325 MHz. Both clock inputs
can be LVDS (see
During the reset phase (RESET_N asserted), both clocks must be stable and running.
This ensures proper reset of the complete device.
Fig 11. LVDS clock configuration
Fig 12. Interfacing CML to LVDS
Figure
CML
Rev. 01 — 26 May 2009
Z = 50
Z = 50
11) but they can also be interfaced with CML (see
Dual 14-bit DAC, up to 650 Msps, 2 and 4 interpolating
LVDS
Z = 50
Z = 50
Zdiff =
100
100 nF
100 nF
V
DDA(1V8)
AGND
1.1 k
2.2 k
Zdiff =
100
CLKN
CLKP
55
55
100 nF
CLKP
CLKN
001aah021
LVDS
DAC1408D650
001aah020
LVDS
© NXP B.V. 2009. All rights reserved.
Figure
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12).