DAC1408D650HW/C1 NXP [NXP Semiconductors], DAC1408D650HW/C1 Datasheet - Page 83
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DAC1408D650HW/C1
Manufacturer Part Number
DAC1408D650HW/C1
Description
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.DAC1408D650HWC1.pdf
(88 pages)
NXP Semiconductors
16. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. SPI timing characteristics . . . . . . . . . . . . . . . .22
Table 11. Interpolation filter coefficients . . . . . . . . . . . . .24
Table 12. Inversion filter coefficients . . . . . . . . . . . . . . . .26
Table 13. DAC transfer function . . . . . . . . . . . . . . . . . . . .26
Table 14. I
Table 15. I
Table 16. Digital offset adjustment . . . . . . . . . . . . . . . . .29
Table 17. Auxiliary DAC transfer function . . . . . . . . . . . .30
Table 18. Page 0 register allocation map . . . . . . . . . . . .36
Table 19. COMMON register (address 00h)
Table 20. TXCFG register (address 01h)
Table 21. PLLCFG register (address 02h)
Table 22. FREQNCO_LSB register (address 03h)
Table 23. FREQNCO_LISB register (address 04h)
Table 24. FREQNCO_UISB register (address 05h)
Table 25. FREQNCO_MSB register (address 06h)
Table 26. PHINCO_LSB register (address 07h)
Table 27. PHINCO_MSB register (address 08h)
Table 28. DAC_A_CFG_1 register (address 09h)
Table 29. DAC_A_CFG_2 register (address 0Ah)
Table 30. DAC_A_CFG_3 register (address 0Bh)
Table 31. DAC_B_CFG_1 register (address 0Ch)
Table 32. DAC_B_CFG_2 register (address 0Dh)
Table 33. DAC_B_CFG_3 register (address 0Eh)
DAC1408D650_1
Objective data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .8
Thermal characteristics . . . . . . . . . . . . . . . . . . .8
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .9
Digital Layer Processing Latency . . . . . . . . . . .15
SYNC_OUT timing . . . . . . . . . . . . . . . . . . . . . .17
Read or Write mode access description . . . . .21
Number of bytes to be transferred . . . . . . . . . .21
bit description . . . . . . . . . . . . . . . . . . . . . . . . .37
bit description . . . . . . . . . . . . . . . . . . . . . . . . .38
bit description . . . . . . . . . . . . . . . . . . . . . . . . .39
bit description . . . . . . . . . . . . . . . . . . . . . . . . .39
bit description . . . . . . . . . . . . . . . . . . . . . . . . .39
bit description . . . . . . . . . . . . . . . . . . . . . . . . .39
bit description . . . . . . . . . . . . . . . . . . . . . . . . .39
bit description . . . . . . . . . . . . . . . . . . . . . . . . .39
bit description . . . . . . . . . . . . . . . . . . . . . . . . .40
bit description . . . . . . . . . . . . . . . . . . . . . . . . .40
bit description . . . . . . . . . . . . . . . . . . . . . . . . .40
bit description . . . . . . . . . . . . . . . . . . . . . . . . .40
bit description . . . . . . . . . . . . . . . . . . . . . . . . .40
bit description . . . . . . . . . . . . . . . . . . . . . . . . .40
bit description . . . . . . . . . . . . . . . . . . . . . . . . .41
O(fs)
O(fs)
coarse adjustment . . . . . . . . . . . . . . . . . .28
fine adjustment . . . . . . . . . . . . . . . . . . . .28
Rev. 01 — 26 May 2009
Dual 14-bit DAC, up to 650 Msps, 2 and 4 interpolating
Table 34. DAC_CFG register (address 0Fh)
Table 35. DAC_A_Aux_MSB register (address 1Ah)
Table 36. DAC_A_Aux_LSB register (address 1Bh)
Table 37. DAC_B_Aux_MSB register (address 1Ch)
Table 38. DAC_B_Aux_LSB register (address 1Dh)
Table 39. Page 2 register allocation map . . . . . . . . . . . . 42
Table 40. MAINCONTROL register (address 00h)
Table 41. MAN_PON register (address 01h)
Table 42. MAN_SUPD register (address 02h)
Table 43. RST_EXT_FCLK register (address 04h)
Table 44. RST_EXT_DCLK register (address 05h)
Table 45. DCSMU_PREDIVCNT register (address 06h)
Table 46. PLL_CHARGETIME register (address 07h)
Table 47. PLL_RUN_IN_TIME register (address 08h)
Table 48. CA_RUN_IN_TIME register (address 09h)
Table 49. IQ_LEVEL_CNTRL register (address 0Ah)
Table 50. IQ_DC_LEVEL_LSB register (address 0Bh)
Table 51. SET_ICHP_PD1 register (address 10h)
Table 52. SET_ICHP_PD2 register (address 11h)
Table 53. SET_ICHP_PFD register (address 12h)
Table 54. SET_RATIO_PD1 register (address 13h)
Table 55. SET_RATIO_PD2 (address 14h)
Table 56. SET_RATIO_PFD register (address 15h)
Table 57. SET_VCM_VOLTAGE register (address 16h)
Table 58. SET_SYNC register (address 17h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 41
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 41
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 41
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 41
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 41
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 46
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 46
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 46
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 46
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 46
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 46
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 46
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 47
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 47
DAC1408D650
© NXP B.V. 2009. All rights reserved.
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