DAC1408D650HW/C1 NXP [NXP Semiconductors], DAC1408D650HW/C1 Datasheet - Page 40

• Manufacturer Part Number: DAC1408D650HW/C1
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1408D650_1
Objective data sheet
Table 27.
Table 28.
Default settings are shown highlighted.
Table 29.
Table 30.
Table 31.
Default settings are shown highlighted.
Table 32.
Bit
7 to 0 PH_NCO[15:8]
Bit
7
6
5 to 0 DAC_A_OFFSET[5:0]
Bit
7 to 6 DAC_A_GAIN_COARSE[7:6] R/W
5 to 0 DAC_A_GAIN_FINE[5:0]
Bit
7 to 6 DAC_A_GAIN_COARSE[9:8] R/W
5 to 0 DAC_A_OFFSET[11:6]
Bit
7
6
5 to 0 DAC_B_OFFSET[5:0]
Bit
7 to 6 DAC_B_GAIN_COARSE[7:6] R/W
5 to 0 DAC_B_GAIN_FINE[5:0]
Symbol
Symbol
DAC_A_PD
DAC_A_SLEEP
Symbol
Symbol
Symbol
DAC_B_PD
DAC_B_SLEEP
Symbol
PHINCO_MSB register (address 08h) bit description
DAC_A_CFG_1 register (address 09h) bit description
DAC_A_CFG_2 register (address 0Ah) bit description
DAC_A_CFG_3 register (address 0Bh) bit description
DAC_B_CFG_1 register (address 0Ch) bit description
DAC_B_CFG_2 register (address 0Dh) bit description
Rev. 01 — 26 May 2009
Access Value Description
R/W
Dual 14-bit DAC, up to 650 Msps, 2 and 4 interpolating
Access Value Description
R/W
R/W
R/W
Access Value Description
R/W
Access Value
R/W
Access Value Description
R/W
R/W
R/W
Access Value Description
R/W
-
0
1
0
1
-
-
-
0
1
0
1
-
-
most significant 8-bits for the NCO phase setting
-
-
DAC A power
DAC A Sleep mode
lower 6-bits for the DAC A offset
on
off
disabled
enabled
least significant 2-bits for the DAC A gain
setting for coarse adjustment
lower 6-bits for the DAC A gain setting for
fine adjustment
DAC B power
DAC B Sleep mode
lower 6-bits for the DAC B offset
less significant 2-bits for the DAC B gain
setting for coarse adjustment
the 6-bits for the DAC B gain setting for
fine adjustment
Description
most significant 2-bits for the DAC A
gain setting for coarse adjustment
most significant 6-bits for the DAC A
offset
on
off
disabled
enabled
DAC1408D650
© NXP B.V. 2009. All rights reserved.
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