mt90503 Zarlink Semiconductor, mt90503 Datasheet - Page 97

• Manufacturer Part Number: mt90503
• Description: 2048vc Aal1 Sar
• Manufacturer: Zarlink Semiconductor

The point generation modules can both be configured for SRTS clock recovery and receive data simultaneously
from 2 VCs. Like adaptive clock recovery, the data is retrieved from the UTOPIA look-up module. The SRTS values
however, are spread over 8 cells. As in the adaptive mode, CRC errors, parity errors and missing cells are reported
to their respective registers (0822h & 0842h [4:0]). This component of the SRTS recovery that receives SRTS data
on a VC from an outside source generates "remote" data
The SRTS clock recovery method requires an accurate external reference clock (f
clock drives the 4-bit counter fnxi_cnt. This count is compared to a count driven by the precise clock digital PLL. In
order to match the interval of 8 SRTS carrying cells, pclk (8 kHz) must be multiplied by K. K is proportional to the
number of frames in the scheduler (P) (375 for fully filled structured AAL1) and inversely proportional to the number
of channels open (Q) (respectively of registers 082Ch and 082Eh for point generation module 0 (adapsrts0)). i.e.,
K=P/Q. This component of the SRTS clock recovery that compares the pclk generated clock with that of the fnxi
clock generates "local" data.
These "local" and "remote" values are written to external memory for the CPU to access.
4.6.7
Similar to the SRTS receive side, the generation of SRTS data must take into account the number of frames in the
scheduler (P of register 0818h) and the number of channels in the VC (Q of register 081Ah). A single VC may be
used to carry SRTS or the SRTS values may be broadcast on multiple VCs. These VCs must, however, be of the
same format, consistent with the master SRTS VC. These VC’s are configured in the Tx SAR (see Table 22 on
page 65).
ref_vcx
AAL1 Byte
SRTS Transmission
pclk
Cells that have
Elimination of
CRC/Parity
bad
Input*
1024
Detection
Time-out
8.192 MHz
Figure 47 - Rx SRTS Clock Recovery Module
Misinserted Cell
Compensation
concatenation
SRTS Value
Lost and
recov_a
recov_b
recov_c
recov_d
recov_e
recov_f
recov_g
recov_h
idclk_a
idclk_b
idclk_c
((P * 1024) / Q)
Zarlink Semiconductor Inc.
Input/
bad_srts_value
srts_value[3:0]
write_now
MT90503
97
8 Cell Pulse
fnxi
RX SRTS Value Writter
(to external memory)
Value Writter
(to external
RX SRTS
memory)
fnxi_cnt[3:0]
To external
control memory
To external
control memory
n
) (e.g., a stratum 3 clock). This
Data Sheet
Local
Remote