mt90503 Zarlink Semiconductor, mt90503 Datasheet - Page 18

• Manufacturer Part Number: mt90503
• Description: 2048vc Aal1 Sar
• Manufacturer: Zarlink Semiconductor

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H.100/H.110 compatible
Low latency TDM bus to TDM bus loopback of up to 2048 channels
Programmable value for the null-octet inserted during an underrun situation
Receive buffer replay capability or silent pattern insertion for underrun situations
Support of CAS and MFS for DS1(ESF) and E1
Automatic Detection of a change in the CAS value, for CAS received in ATM cells, and CAS received from
TDM bus
SRTS clock recovery:
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Adaptive clock recovery
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Direct 8 kHz clock recovery:
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Can generate a 20 MHz clock for an external PLL, e.g. MT9042 or MT9044 (output on one of the
multipurpose timing reference pins)
Supports AAL1 (with pointer, or without pointer byte), CBR-AAL0, and CBR-AAL5 (AAL5-VTOA) Cell formats
Supports partially filled cells, with fills from 4 to 47 bytes
AAL1 cell format for “Structured DS1/E1 Nx64 Kbit/s Service” as per ATM Forum AF-VTOA-0078.000
“Circuit Emulation Services Interoperability Specification” (Nx64 Basic Service, DS1 Nx64 Service with CAS,
and E1 Nx64 Service with CAS)
VCs carrying 1 to 2048 TDM channels
TDM to ATM Transmission latency less than 250 s (when minimum voice latency desired, and strict
multiframe alignment of voice with CAS not required)
TDM to ATM Transmission latency less than 3.25 ms (when strict multiframe alignment of voice with CAS
required)
ATM to TDM Reception latency less than CDV + 250 s (when minimum voice latency desired, and strict
multiframe alignment of voice with CAS not required)
ATM to TDM Reception latency less than CDV + 6.250 ms (when strict multiframe alignment of voice with
CAS required)
Per VCC monitoring (Receive/Reassembly direction):
TDM Interface
Clock Recovery
ATM SAR
Dual reference VCs (for redundancy)
Broadcast SRTS VCs in Transmit /Segmentation direction
Dual reference VCs (for redundancy)
Limited jitter, precision enhanced, MCLK (chip clock) to 8 kHz dividers
Can generate an 8 kHz reference using one of 8 multipurpose timing reference pins
Supports all n * 8 kHz input reference, (1.544 MHz, 2.048 MHz, 19.44 MHz, etc.) up to 12500 * 8 kHz
Output high time and low time of the 8 kHz reference output can be modified relative to input signal
The eight multipurpose timing reference pins can be used to support many possible clock recovery
configurations, including the following reference signals: SEC8K (MVIP), ATM8K (to/from PHY25 or from
PHY155), FNXI (SRTS), CT_NETREF (for CT-Bus)
Zarlink Semiconductor Inc.
MT90503
18
Data Sheet