mt90503 Zarlink Semiconductor, mt90503 Datasheet - Page 42

• Manufacturer Part Number: mt90503
• Description: 2048vc Aal1 Sar
• Manufacturer: Zarlink Semiconductor

The TDM interface is capable of looping back up to 2048 TSSTs with a latency of two TDM frames, or 250 s. This
loopback is indicated by the control structures associated to each TSST. The loopback allows any two time-slots
and streams to be connected together, and work independently of the speed of each of the streams.
The MT90503 can interface with 32 data streams as mentioned in previous paragraphs. Since each TSST can be
used to either send or receive data, the MT90503 must tri-state the CT_D pins that are receiving data. To avoid
overlap between a sending and a receiving TSST, this must be done before the next one begins.
4.2.2
The MT90503 can operate as either a primary or secondary H.100/H.110 master clock source. The H.100/H.110
clock (CT_C8) is driven by either CT_C8_A or CT_C8_B. The MT90503 can generate the primary bus clock and all
its associated bus clocks (ct_fr_comp, sclk, sclkx2, CT_C16-, CT_C16+, CT_C2 and CT_C4) by using the
CT_NETREF signal. The CT_NETREF may be received from another H.100/H.110 bus compatible device or it can
be determined by the clock recovery module. In master mode, the MT90503 will generate all the compatibility
clocks that are necessary for communicating with MVIP and SCSA TDM interfaces. These include the FR_COMP,
C2, C4 and C16 signals for communicating with MVIP buses, and the SCLK and SCLKx2 signals for
communicating with Signal Computing System Architecture SCSA buses.
The TDM module monitors both CT_C8_A and CT_C8_B signals for clock properties and failure. In every
operating mode, both the CT_C8_A and CT_C8_B signals are monitored for clock failure. There are two methods
of detecting a clock failure on the bus. Firstly, if the rising edge of the clock does not appear within
of the expected period, the clock is flagged as being invalid. Secondly, if a single frame does not contain exactly
1024 clock cycles, then the clock will fail.
The MT90503 can be configured to switch to the backup master clock (CT_C8_A or CT_C8_B), upon the detection
of a master clock failure. The MT90503 can be programmed as a secondary master and therefore switch to the
backup master clock when the external primary master clock source has failed. If the MT90503 switches from a
secondary master to master it will re-synchronise the TDM module with the backup clock and generate the
compatibility clocks. The MT90503 continually monitors both CT_C8_A and CT_C8_B clocks for a failure condition.
The MT90503 can be programmed to automatically switch to its backup clock in case of a failure.
The MT90503 is an H.100/H.110 master-capable device and, therefore, is able to generate both CT_C8 clocks and
CT_FRAME and compatibility signals. As long as the primary signals on the bus are valid, the MT90503 will
synchronise its output to them using a PLL. The MT90503 can also generate the CT_C8 and CT_FRAME signals
independently of the PLL, using the local 16 MHz clock. In this case, the output signals have no phase relation with
those present on the bus.
When the TDM bus interface module has written the received data to the circular buffers, it increments the
Time-Slot Memory Pointer that is sent to the TX_SAR.
4.2.3
When writing to the external data memory, no return value is expected. However, when reading data, a return value,
upon storing the data into an RX TSST, is expected and is required to be written back to the structure memory. The
underrun count, which may or may not have been updated, is always written back along with all the other bits of the
second word.
When the data is received at the time slot memory, it is sent via the TDM datapath to the external data memory.
According to which time slot is currently being used, the TDM control structures are read.
TDM Bus Clocking Mechanism
TDM Datapath
Zarlink Semiconductor Inc.
MT90503
42

Data Sheet
35 ns window