mt90503 Zarlink Semiconductor, mt90503 Datasheet - Page 119

• Manufacturer Part Number: mt90503
• Description: 2048vc Aal1 Sar
• Manufacturer: Zarlink Semiconductor

Address: 236h
Label: utopia_genc
Reset Value: 0001h
Address: 240h
Label: cmem_parity0
Reset Value: 0000h
cmem_parity_generation_data_mask
Address: 242h
Label: cmem_parity1
Reset Value: 0000h
cmem_parity_generation_add_mask
cmem_parity_generation_add_mask
utopia_clk_divisor_resetc
cmem_parity_conf[1:0]
reserved
Label
reserved
[18:16]
Label
[15:0]
Label
Table 62 - Utopia Clock Generation C Register
Table 63 - Control Memory Parity0 Register
Table 64 - Control Memory Parity1 Register
Position
15:12
Bit
11
Position
Position
15:0
15:8
Bit
1:0
4:2
7:5
Bit
Zarlink Semiconductor Inc.
Type
RW
RW
MT90503
Type
Type
RW
RW
RW
RW
RO
119
When ’0’, the clock divisor module is held in reset.
Reserved. Must always be "0000"
0' = parity bits; '1' = user data. In normal chip
operation, this field should be set to "00", because
the chip does not use the parity bits of the control
memory.
Mask of address bits [18:16] to be used to generate
parity for the control memory. A '1' in one of these
bits indicates that the corresponding address bit will
be used to generate parity.
Reserved. Must always be "0000"
Mask of data bits to be used to generate parity for
the control memory. A '1' in one of these bits
indicates that the data bit will be used to generate
parity.
Mask of address bits [15:0] to be used to generate
parity for the control memory. A '1' in one of these
bits indicates that the corresponding address bit
will be used to generate parity.
Description
Description
Description
Data Sheet