mt90503 Zarlink Semiconductor, mt90503 Datasheet - Page 86

• Manufacturer Part Number: mt90503
• Description: 2048vc Aal1 Sar
• Manufacturer: Zarlink Semiconductor

4.5.8
The UTOPIA module contains the ability to prevent cells in the 4-cell input FIFOs (RXA, RXB, RXC, and TX_SAR)
from being handled by the UTOPIA module in the case that the 32-cell output FIFOs (TXA, TXB, TXC, and
RX_SAR) exceed programmable levels.
An input FIFO will be blocked when the level of any output FIFO exceeds the level set for that combination of output
FIFO and input FIFO. The levels can be set independently to 1 to 31 cells or to 0, which means no flow control will
be exerted (see registers 0338h-033Ah, 0358h-035Ah, 0378h-037Ah). Cell arrival counters and cell departure
counters for each port, stored in registers (0330h-0336h, 0350h-0356h, 0370-0376h, 0390-0396h), are used to
monitor the fill levels of each output FIFO.
4.5.9
Due to the different possible configurations of the UTOPIA ports, the functions of some pins change, depending on
the configuration. Some unused data pins when port A and/or port B are in 8-bit mode become general purpose
inputs and/or outputs. When Level-2 addressing is in place for port A, portions of the port B data buses are used for
as port A addressing pins. The function of the clav (cell available) and enb (enable data transfer) pins alternate
when the port is in ATM mode or PHY mode (Figure 42 on page 87).
Please note that the I/O direction of the pins remains the same.
UTOPIA Flow Control
External Interface Signals
fast_clk
rxa_clk
rxb_clk
txa_clk
txb_clk
rxc_clk
txc_clk
mclk
Figure 41 - UTOPIA Clock Generation
utopia_clk_1
utopia_clk_2
utopia_clk_3
Zarlink Semiconductor Inc.
One of three UTOPIA clock generators
Divider by n
(n=1 to 16)
MT90503
One of six UTOPIA Clocks
86
Inversion
rxa_clk
utopia_clk_1
Data Sheet