mt90503 Zarlink Semiconductor, mt90503 Datasheet - Page 216

• Manufacturer Part Number: mt90503
• Description: 2048vc Aal1 Sar
• Manufacturer: Zarlink Semiconductor

Note: t1, t4, and t5 are dependent upon the last of inmo_cs and inmo_rd_ds to be asserted. t6, and t10 are
dependent on the first of inmo_cs and inmo_rd_ds to be de-asserted.
Symbol
t10
t12
t11
t3
t4
t5
t6
t7
t9
Notes:
write_active = (inmo_cs = 0) AND (inmo_ds = 0) AND (inmo_r/w = 0)
inmo_d[15:0]
write_active
Address Hold -- inmo_rdy_ndtack low to
inmo_a[14:0] and inmo_a_das invalid
Inmo_rdy_ndtack high -- inmo_cs and inmo_rd_ds
asserted to inmo_rdy_ndtack driving one
Inmo_rdy_ndtack delay -- inmo_cs and inmo_rd_ds
asserted to inmo_rdy_ndtack asserted
Inmo_rdy_ndtack hold -- inmo_cs or inmo_rd_ds
de-asserted to inmo_rdy_ndtack driving one
Inmo_rdy_ndtack high impedance --
inmo_rdy_ndtack driving one to inmo_rdy_ndtack
high-impedance
Data to inmo_rdy_ndtack delay -- inmo_d[15:0] valid
to inmo_rdy_ndtack asserted
Data output hold -- inmo_cs or inmo_rd_ds
de-asserted to inmo_d[15:0] invalid
R/W setup -- R/W asserted to inmo_cs asserted
R/W hold -- inmo_cs deasserted to R/W deasserted
inmo_ale
inmo_rdy
Table 298 - Non-multiplexed CPU Interface Motorola Mode (continued)
Figure 58 - Multiplexed CPU Interface Write Access - Motorola Mode
Description Write Access
t10
t9
t8
t1
Address
Valid
t11
t2
Zarlink Semiconductor Inc.
MT90503
216
t5
mclk_src - 4
Data Valid
Min.
0
0
0
2
0
0
0
t4
Typ.
t3
t6
See Table 300
t7
Max.
12
10
10
8
Data Sheet
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns