mt90503 Zarlink Semiconductor, mt90503 Datasheet - Page 104

• Manufacturer Part Number: mt90503
• Description: 2048vc Aal1 Sar
• Manufacturer: Zarlink Semiconductor

5.5
5.5.1
Address: 100h
Label: control
Reset Value: 0000h
nreset_rxa_clk_mclk_src
nreset_rxb_clk_mclk_src
nreset_txa_clk_mclk_src
nreset_txb_clk_mclk_src
nreset_txc_clk_mclk_src
nreset_rxc_clk_mclk_src
mem_clk_pecl_enable
nreset_chip_mclk_src
write_cache_enable
mem_clk_o_enable
mem_clk_input_sel
nreset_registers
Detailed Register Description
test_status
CPU Registers
reserved
reserved
reserved
Label
Position
Bit
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
Table 37 - CPU Control Register
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
TS
Zarlink Semiconductor Inc.
MT90503
Controls the reset for the MAINREG module and certain CPU
functions. '1' out of reset. '0' in reset. Should not be removed
unless mclk is present.
Resets all other parts of the chip. '1' out of reset. '0' in reset. Should
not be removed unless mclk is present.
nreset for UTOPIA TXA clock (syncronized on mclk_src). This
reset should not be removed unless the corresponding clock is
present.
nreset for UTOPIA TXB clock (syncronized on mclk_src). This
reset should not be removed unless the corresponding clock is
present.
nreset for UTOPIA TXC clock (syncronized on mclk_src). This
reset should not be removed unless the corresponding clock is
present.
nreset for UTOPIA RXA clock (syncronized on mclk_src). This
reset should not be removed unless the corresponding clock is
present.
nreset for UTOPIA RXB clock (syncronized on mclk_src). This
reset should not be removed unless the corresponding clock is
present.
nreset for UTOPIA RXC clock (syncronized on mclk_src). This
reset should not be removed unless the corresponding clock is
present.
For future use: reserved for mem_clk oe (TTL)
For future use: reserved for PECL oe
Enables the mem_clk TTL output to toggle, active high
Enables the mem_clk PECL output to toggle, active high
'0' = mem_clk_i pin, '1' = mem_clk PECL pins
When '0', only 1 access can be treated at a time. When '1', write
cache contains 128 accesses. If this bit is '1', the average latency
to perform a write will be reduced, but the worst-case latency will
be increased.
Reserved. Must be set t o "0".
When '1', all the status bits in the register will be set.
104
Description
Data Sheet