mt90503 Zarlink Semiconductor, mt90503 Datasheet - Page 84

• Manufacturer Part Number: mt90503
• Description: 2048vc Aal1 Sar
• Manufacturer: Zarlink Semiconductor

Unknown non-OAM cells and/or unknown OAM cells can be discarded or directed to one or more output FIFOs. All
unknown non-OAM cells from a port are discarded or directed to the same location(s) and all unknown OAM cells
from a port are discarded or directed to the same location(s). Unknown cells can be directed differently for each port
on which they were received. Unknown cells cannot be sent to the SAR portion of the RX_SAR. The routing of
unknown cells is set in registers 03A2h and 03A4h.
Known cells are handled according to the LUT (Look-Up Table) entry for the cell’s VPI/VCI.
4.5.6.1
LUT entries direct cells with known VPI/VCIs to either be discarded or placed in one or more of five possible
destinations: the four output FIFOs and the data cell FIFO in external control memory, by way of the RX_SAR FIFO.
OAM cells can be directed independently of non-OAM cells with the same VPI/VCI. OAM cells cannot be directed to
the SAR portion of the RX_SAR.
LUT entries can be either 4- or 8-bytes long (short or long LUT entries, set in register 302h). All look-up table
entries in all three LUTs are the same size. 8-byte entries are only required if header translation is to be performed
for one or more VCs. Cells undergoing header translation have their NNI bits, the remaining VPI bits and/or the VCI
bits replaced by the corresponding bits in the LUT entry and are then either discarded or sent to one or more of the
possible destinations. VCs that undergo header translation are not directed to the SAR portion of the RX_SAR.
Clock recovery information can be gathered from up to two VCs by setting bit A in one LUT entry and bit B in the
same or another LUT entry. A maximum of one VC can have bit A set and a maximum of one VC can have bit B set.
4.5.6.2
A LUT base address exists for each of the three ports (registers 0320h, 0340h, 0360h). The LUT base addresses
for two or more ports can be the same. An identifier for a VC is created by concatenating any number of LSBs from
the VPI and LSBs from the VCI, to a maximum of 16 bits. The number of VCI bits used is programmed in registers
0324h, 0344h and 0364h for Port A, B, C respectively. The total number of bits in the identifier is programmed in
registers 0322h, 0342h and 0362h for Port A, B and C respectively.The identifier is then appended with either two
or three zeros (for either short or long LUT entries).
+0
+2
+0
+2
+4
+6
Note: If chip is configured for long LUT
entries, non-header translation LUT entries
are followed by two reserved words.
b15 b14 b13 b12 b11 b10 b9 b8
b15 b14 b13 b12 b11 b10 b9 b8
NNI VPI VCI A
0
VPI[11:8]
Reserved
0
Look-Up Tables Entries
LUT Addressing
0
Non-header translation LUT Entry Format
LUT Entry Format for Header Translation
A
B
B
VCI[11:0]
RX Structure Pointer
VPI[7:0]
Figure 39 - Short and Long Look-Up Table Entries
b7 b6
b7 b6
NCR
NCR
b5
b5
b4 b3
b4 b3
Zarlink Semiconductor Inc.
VCI[15:12]
b2
OCR
b2
OCR
MT90503
b1
b1
b0
84
b0
NNI: When ’1’ the VPI[11:8] field in each cell for this LUT entry will
be replaced by the VPI[11:8] contained in this entry.
VPI: When ’1’ the VPI[7:0] field in each cell for this LUT entry will
be replaced by the VPI[7:0] contained in this entry.
VCI: When ’1’ the VCI[15:0] field in each cell for this LUT entry will
be replaced by the VCI[15:0] contained in this entry.
A, B: Adaptive/SRTS Clock Recovery VC A or VC B. Only one
VC can have bit A set. Only one VC can have bit B set.
NCR: Normal (non-OAM) Cell Routing
memory) via the RX_SAR
memory) via the RX_SAR
’00000’ = discard
’xxxx1’ = send to TXA port
’xxx1x’ = send to TXB port
’xx1xx’ = send to TXC port
’x1xxx’ = send to data cell FIFO (in external control
’1xxxx’ = send to SAR portion of the RX_SAR
OCR: OAM Cell Routing
’0000’ = discard
’xxx1’ = send to TXA port
’xx1x’ = send to TXB port
’x1xx’ = send to TXC port
’1xxx’ = send to data cell FIFO (in external control
Data Sheet