mt90503 Zarlink Semiconductor, mt90503 Datasheet - Page 203

• Manufacturer Part Number: mt90503
• Description: 2048vc Aal1 Sar
• Manufacturer: Zarlink Semiconductor

6.0
6.1
Underrun counter: 16-bit counter that counts the number of underruns detected by TDM interface.
6.2
Percentage of bandwidth utilisation: a register (0510h) which indicates how many mclk cycles were required to treat
the last frame.
Transmitted Cell Counter: 32-bit counter that counts the number of cells transmitted on a particular VC. Each VC
has its own counter in its structure.
6.3
Error reporting structures allow software-based counters for the following errors:
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Address: A0Ch
Label: status_ie
Reset Value: 0000h
h100_frame_a_bad_rol
h100_frame_b_bad_rol
h100_clk_a_bad_rol
h100_clk_b_bad_rol
P-byte absent error
P-byte framing error
P-byte range error
P-byte parity error
Overrun error
Underrun error
AAL1 CRC error
AAL1 parity error
Single cell loss
Multiple cell loss
Cell misinsertion
TDM statistics
TX SAR statistics
RX SAR statistics
Statistics
reserved
Label
Position
15:4
Bit
0
1
2
3
Table 291 - H.100 Interrupt Enable Register
Type
IE
IE
IE
IE
IE
Zarlink Semiconductor Inc.
When '1' and the corresponding status bit is '1', an interrupt will
be generated.
When '1' and the corresponding status bit is '1', an interrupt will
be generated.
When '1' and the corresponding status bit is '1', an interrupt will
be generated.
When '1' and the corresponding status bit is '1', an interrupt will
be generated.
Reserved. Always read as "0000_0000_0000"
MT90503
203
Description
Data Sheet