mt90503 Zarlink Semiconductor, mt90503 Datasheet - Page 96

• Manufacturer Part Number: mt90503
• Description: 2048vc Aal1 Sar
• Manufacturer: Zarlink Semiconductor

The point recording portion of the module records three fields. The ’number of the cell’ is a 32-bit field, the ’number
of mclk cycles’ counted at time of cell arrival is a 32-bit field and the ’number of pclk cycles’ counted when the cell
received is a 48-bit field composed of a 32-bit integer and 16-bit fraction. This information, from the three counters
(cell, mclk and pclk), 112 bits in total, is written to external control memory in a circular buffer reserved for clock
recovery information. (See External Memory Point Format on page 98.) Ratios of this data are compared by the
clock recovery algorithm to the desired ratios and correspondingly, corrections are made to the pclk frequency
dividers.
It is possible to eliminate some of the timing reference cells sent to memory. This may be done in order to conserve
processing power. It is especially useful if the clock recovery VC has a high number of channels (i.e. a high rate of
cell arrival). The 8-bit registers, adap_pnt_elim_x (082Ah and 084Ah) can be programmed to "keep one point out of
X".
Each adaptive module has its own associated pclk generator, allowing the wander of each VC to be tracked with
respect to the pclk frequency.
4.6.6.1
The Synchronous Residual Time Stamp (SRTS) method of clock recovery is standardised in ITU-T I.363.1, ANSI
T1.630 and Bellcore’s patent
The SRTS method uses a stream of residual time stamps (RTS) to express the difference between a common
reference clock (f
1. Zarlink has entered into an agreement with Bellcore with respect to Bellcore’s U.S. Patent No. 5,260,978 and Zarlink’s manufacture and sale
of products containing the SRTS function. However the purchase of this product does not grant the purchaser any rights under U.S. Patent
No. 5,260,978. Use of this product or its resale as a component of another product may require a license under the patent which is available
from Bell Communications Research, Inc., 445 South Street, Morristown, New Jersey 07960.
SRTS Clock Recovery
n
) and a local service clock (f
1
(U.S. Patent 5 260 978 (11/93)).
Discard Cell
(multiple cell loss detected)
SecLast SN + 2
SN = Last SN -
and CRC OK
1 & Last SN =
Figure 46 - Adaptive Cell Reception Flow
AAL1 Byte
SN = Last
SN = Last
Parity OK
Yes
No
SN + 2
SN + 1
No
No
s
Zarlink Semiconductor Inc.
- derived from the local TDM clock, ct_c8_x).
Yes
Yes
Yes
No
MT90503
Generate two ’ref_vcx’ pulses
(lost cell detected)
Discard Cell
(misinserted cell detected)
Generate ’ref_vcx’ pulse
96
Discard Cell
Data Sheet