mt90503 Zarlink Semiconductor, mt90503 Datasheet - Page 95

• Manufacturer Part Number: mt90503
• Description: 2048vc Aal1 Sar
• Manufacturer: Zarlink Semiconductor

4.6.6
Adaptive clock recovery is a method which generates a clock based on the rate at which AAL1 cells are arriving.
The device acting as the master does not have to structure its cells differently or add any information, it simply
transmits CBR data in AAL1 cells. The slave device performs the adaptive clock recovery, based on a clock
recovery algorithm using points placed in external memory by the point generation module.
To perform adaptive clock recovery, the point generation module of the MT90503 is normally configured with the
cell arrival event (ref_vca or ref_vcb) as its timing reference (source 0x20 or 0x21 of Table 28, “Source Selection,”
on page 89). The VC’s which are defined as vca and vcb are recorded in the UTOPIA LUT (see Figure 39 on
page 84). The input multiplexer gives the flexibility to use any clock desired. The cell arrival event is received
directly from the UTOPIA look-up module. The look-up engine generates a VC-specific pulse and passes on the
AAL1 byte of the received cell.
The AAL1 byte is composed of a sequence number (SN), CRC-3 sequence number protection (SNP) and a parity
bit. The adaptive module checks for CRC and parity errors. If errors are found, the cell is ignored and the
appropriate bit of register 0822h or 0842h is flagged. The sequence number is also verified to determine if cells
have been lost. Single cell losses can be compensated for and the single_cell_lost register bit (0822h or 0842h [2])
will be set. Multiple cell losses cannot be compensated, but will be flagged as either multi_cell_lost (0822h or 0842h
[3]) or cell_misinserted (0822h or 0842h [4]).
AAL1 byte
ref_vca
ref_vcb
Adaptive Clock Recovery
compensation for
CRC or parity,
Elimination of
cells with bad
ref_input_select
lost cells
lost_cell_pulse
valid_cell_pulse
Detection
Time-out
Cell Counter
Figure 45 - Adaptive Clock Recovery
Zarlink Semiconductor Inc.
pclk_integer[31:0]
pclk_fraction[15:0]
cell_counter
[31:0]
MT90503
pclk_div pclk_frc
95
Counter
Precise Clock Generator
pclk
Point Generation Process
From Registers
pclk
load_divisor_now
Counter
mclk
mclk_counter[31:0]
(keeps 1 point out
Point Elimination
of x cells)
Write Points to
External Control
Memory
Data Sheet