mt90503 Zarlink Semiconductor, mt90503 Datasheet - Page 209

• Manufacturer Part Number: mt90503
• Description: 2048vc Aal1 Sar
• Manufacturer: Zarlink Semiconductor

DC Characteristics (continued)
8.1.1
Latch-up is not a concern during power sequencing. The only requirement for sequencing 3.3 V and 5 V supplies
during power up is that the MT90503 be either held in reset until the rails are stable or have its global_tri_state pin
held low (tristate). However, to minimise over-voltage stress during system start-up, the 3.3 V supply applied to the
MT90503 should be brought to a level of at least V
equal to 3.3 V. This practice can be implemented either by ensuring that the 3.3 V power turns on simultaneously
with or before the system 5 V supply turns on, or by ensuring that all 5 V signals are held to a logic LOW state
during the time that V
3.0 V.
Regardless of the method chosen to limit over-voltage stress during power up, exposure must be limited to no more
than + 6.5 V input voltage (V
prevent bus contention.
8.1.2
Latch-up is not a concern in power failure mode. Although extended exposure of the MT90503 to 5 V signals during
3.3 V supply power failure is not recommended, there are no restrictions as long as V
absolute maximum rating of 6.5 V. To minimise over-voltage stress during a 3.3 V power supply failure, the designer
should either link the power supplies to prevent this condition or ensure that all 5 V signals connected to the
MT90503 are held in a logic LOW state until the 5 V supply is deactivated.
8.1.3
Pull-ups from the 5 V rail to 3.3 V (5 V tolerant) outputs of the MT90503 can cause reverse leakage currents into
those 3.3V outputs when they are active HIGH. (No significant reverse current is present during the high
impedance state.) If the application can put the MT90503 in a state where MCLK is stopped, and a large number of
3.3 V output buffers are held in a static HIGH state, current can flow from the 5 V rail to the 3.3 V rail. If this
MCLK-stopped state can not be avoided, the user should determine if the total MT90503 reverse current will have a
negative impact on the system 3.3 V power supply. Alternatively, the global_tri_state pin of the MT90503 can be
asserted low to put all outputs in the high impedance state.
8.2
As the MT90503 has a diode clamp to the 5 V rail, the diode clamp must be no more than 0.7 V below V
the pin is not tristated. This can be accomplished by asserting the global_tri_state pin low or by keeping the
MT90503 in reset until all rails are stable.
b. T
Voltage measurements are with respect to ground (V
21
22
OP
H.110 Diode Clamp Rail
= 0  C to 70  C; V
3.3V output LOW current (12
mA buffer)
Junction-to-Ambient Thermal
Resistance
Precautions During Power Sequencing
Precautions During Power Failure
Pull-ups
DD
DD
= 3.3V  5%
< 3.0 V. This condition is also met also if the MT90503 is held in reset until V
IN
). The global_tri_state pin of the MT90503 can be asserted low on power-up to

I
OL
J-A
SS
Zarlink Semiconductor Inc.
) unless otherwise stated.
MT90503
DD
= 3.0 V before a signal line is driven to a level greater than or
209
14.225
12.0
C/W
mA
IN
0 cfm air flow
(natural convection
airflow only)
V
does not exceed the
OL
= 0.4 V
Data Sheet
DD
DD
reaches
when