mt90503 Zarlink Semiconductor, mt90503 Datasheet - Page 17

• Manufacturer Part Number: mt90503
• Description: 2048vc Aal1 Sar
• Manufacturer: Zarlink Semiconductor

Figure 4 shows the dataflow from the RX UTOPA interface to the H.100/H.110 bus.
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H.100/H.110 Bus
Contains 3 UTOPIA ports with transmit and receive interfaces:
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Supports cell switching through daisy chained SAR/PHY devices via the UTOPIA interface (AAL5 SARs,
AAL1 SARs such as MT90503, and AAL2 SARs such as MT90502).
Supports both UNI and NNI header formats
Supports any combination of VCI/VPI concatenation up to 16 bits in ATM Receive direction
Supports up to 65536 Virtual Circuits Per UTOPIA Port in ATM Receive direction
Rapid timing reference cell processing in Receive/Segmentation direction
Can eliminate null cells (VPI = 0, VCI = 0) received at UTOPIA A, B, and C port inputs
Filters received cells before accessing VCC Look Up Table (LUT)
UTOPIA VCC loopback for bi-directional ring functionality (from RX A to TX B and from RX B to TX A)
Per-VCC User cell and OAM cell destination control (for VCs that have a LUT entry)
Per-UTOPIA-port User cell and OAM cell destination control (for VCs that do not have a LUT entry)
UTOPIA Interface
Port A: 16-bit or 8-bit UTOPIA Level 2, ATM mode (single-PHY) or PHY mode (single or multi-PHY). Accepts
data rates up to 622 Mb/s.
Port B: 16-bit or 8-bit UTOPIA Level 2 without bus addressing, ATM mode or PHY mode (restricted to 8-bit
when Port A is in multi-PHY mode). Accepts data rates up to 622 Mb/s.
Port C: 8-bit UTOPIA, ATM mode or PHY mode
Features Detailed Description
CPU
RX UTOPIA
Interface
Path Controlled by TDM Module
TDM Bus
UTOPIA Input FIFO
Figure 4 - Receive Data Flow - UTOPIA to TDM
Time-Slot Memories
CPU Module
Zarlink Semiconductor Inc.
MT90503
Path Controlled by UTOPIA Module
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(External Data Memory)
Circular Buffers[7:0]
UTOPIA Cell Router
External Control
Path Controlled by RX SAR Module
Memory
UTOPIA Output FIFO
RX SAR CBR Portion
RX SAR non-CBR
Portion
Data Sheet