mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 98

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Table 44:
PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
From Command
WRITE with auto
precharge
(Bank n)
WRITE Using Concurrent Auto Precharge
READ or READ with auto precharge
Data for any WRITE burst may be concatenated with a subsequent WRITE command to
provide continuous flow of input data. The first data element from the new burst is
applied after the last element of a completed burst. The new WRITE command should
be issued x cycles after the first WRITE command, where x equals BL/2.
Figure 60 on page 100 provides examples of concatenated bursts of BL = 4 and how full-
speed random write accesses within a page or pages can be performed. An example of
nonconsecutive WRITEs is shown in Figure 61 on page 100. DDR2 SDRAM supports
concurrent auto precharge options, as shown in Table 44 on page 98.
DDR2 SDRAM does not allow interrupting or truncating any WRITE burst using BL = 4
operation. Once the BL = 4 WRITE command is registered, it must be allowed to
complete the entire WRITE burst cycle. However, a WRITE BL = 8 operation (with auto
precharge disabled) might be interrupted and truncated only by another WRITE burst as
long as the interruption occurs on a 4-bit boundary due to the 4n-prefetch architecture
of DDR2 SDRAM. WRITE burst BL = 8 operations may not be interrupted or truncated
with any command except another WRITE command, as shown in Figure 62 on
page 101.
Data for any WRITE burst may be followed by a subsequent READ command. To follow a
WRITE,
cycles required to meet
WRITE burst may be followed by a subsequent PRECHARGE command.
met, as shown in Figure 64 on page 103.
less of the data mask condition.
WRITE or WRITE with auto
PRECHARGE or ACTIVATE
t
To Command
WTR should be met, as shown in Figure 63 on page 102. The number of clock
precharge
(Bank m)
t
WTR is either 2 or
98
(with Concurrent Auto Precharge)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
WR starts at the end of the data burst, regard-
(CL - 1) + (BL/2) +
t
WTR/
Minimum Delay
1Gb: x4, x8, x16 DDR2 SDRAM
t
(BL/2)
CK, whichever is greater. Data for any
1
t
WTR
©2003 Micron Technology, Inc. All rights reserved.
t
WR must be
Operations
Units
t
t
t
CK
CK
CK