mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 110

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Power-Down Mode
PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
DDR2 SDRAMs support multiple power-down modes that allow significant power
savings over normal operating modes. CKE is used to enter and exit different power-
down modes. Power-down entry and exit timings are shown in Figure 71 on page 111.
Detailed power-down entry conditions are shown in Figures 72–79. The CKE Truth Table,
Table 45, is shown on page 112.
DDR2 SDRAMs require CKE to be registered HIGH (active) at all times that an access is
in progress—from the issuing of a READ or WRITE command until completion of the
burst. Thus, a clock suspend is not supported. For READs, a burst completion is defined
when the read postamble is satisfied; for WRITEs, a burst completion is defined when
the write postamble and
READ command) are satisfied, as shown in Figures 74 and 75 on page 114. The number
of clock cycles required to meet
Power-down mode (see Figure 71 on page 111) is entered when CKE is registered LOW
coincident with a NOP or DESELECT command. CKE is not allowed to go LOW during a
mode register or extended mode register command time, or while a READ or WRITE
operation is in progress. If power-down occurs when all banks are idle, this mode is
referred to as precharge power-down. If power-down occurs when there is a row active in
any bank, this mode is referred to as active power-down. Entering power-down deacti-
vates the input and output buffers, excluding CK, CK#, ODT, and CKE. For maximum
power savings, the DLL is frozen during precharge power-down. Exiting active power-
down requires the device to be at the same voltage and frequency as when it entered
power-down. Exiting precharge power-down requires the device to be at the same
voltage as when it entered power-down; however, the clock frequency is allowed to
change (see "Precharge Power-Down Clock Frequency Change" on page 116).
The maximum duration for either active or precharge power-down is limited by the
refresh requirements of the device
entry and exit is limited by the
tained while in power-down mode: CKE LOW, a stable clock signal, and stable power
supply signals at the inputs of the DDR2 SDRAM. All other input signals are “Don’t Care”
except ODT. Detailed ODT timing diagrams for different power-down modes are shown
in Figure 82 on page 121–Figure 89 on page 125.
The power-down state is synchronously exited when CKE is registered HIGH (in
conjunction with a NOP or DESELECT command), as shown in Figure 71 on page 111.
t
WR (WRITE-to-PRECHARGE command) or
110
t
CKE (MIN) parameter. The following must be main-
t
WTR is either two or
t
RFC (MAX). The minimum duration for power-down
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1Gb: x4, x8, x16 DDR2 SDRAM
t
WTR/
t
CK, whichever is greater.
©2003 Micron Technology, Inc. All rights reserved.
t
WTR (WRITE-to-
Operations