mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 103

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 64:
PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
Command
DQS#, DQS
DQS#, DQS
DQS#, DQS
Address
t DQSS (NOM)
t DQSS (MIN)
t DQSS (MAX)
CK#
CK
DM
DM
DM
DQ
DQ
DQ
Bank a,
WRITE-to-PRECHARGE
WRITE
Col b
T0
Notes:
WL - t DQSS
WL + t DQSS
WL + t DQSS
1. Subsequent rising DQS signals must align to the clock within
2. DI b = data-in for column b.
3. Three subsequent elements of data-in are applied in the programmed order following DI b.
4. BL = 4, CL = 3, AL = 0; thus, WL = 2.
5.
6. The PRECHARGE and WRITE commands are to the same bank. However, the PRECHARGE
7. A10 is LOW with the WRITE command (auto precharge is disabled).
NOP
T1
t
and WRITE commands may be to different banks, in which case
PRECHARGE command could be applied earlier.
WR is referenced from the first positive CK edge after the last data-in pair.
DI
b
NOP
T2
DI
b
DI
b
T2n
1
NOP
1
T3
103
1
T3n
T4
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1Gb: x4, x8, x16 DDR2 SDRAM
T5
NOP
Transitioning Data
t
DQSS.
t WR
t
©2003 Micron Technology, Inc. All rights reserved.
WR is not required and the
T6
NOP
Operations
(a or all)
Bank,
T7
PRE
Don’t Care
t RP