mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 101

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 62:
PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
DQS, DQS#
Command
Address
CK#
A10
DQ
CK
WRITE 1 a
Valid 5
T0
WRITE Interrupted by WRITE
2-clock requirement
Notes:
NOP 2
T1
WL = 3
1. BL = 8 required and auto precharge must be disabled (A10 = LOW).
2. The NOP or COMMAND INHIBIT commands are valid. The PRECHARGE command cannot be
3. The interrupting WRITE command must be issued exactly 2 ×
4. The earliest WRITE-to-PRECHARGE timing for WRITE at T0 is WL + BL/2 +
5. The WRITE command can be issued to any valid bank and row address (WRITE command at
6. Auto precharge can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the inter-
7. Subsequent rising DQS signals must align to the clock within
8. Example shown uses AL = 0; CL = 4, BL = 8.
issued to banks used for WRITEs at T0 and T2.
starts with T7 and not T5 (because BL = 8 from MR and not the truncated length).
T0 and T2 can be either same bank or different bank).
rupting WRITE command.
WRITE 3 b
Valid 6
Valid 5
T2
NOP 2
T3
DI
a
WL = 3
a + 1
DI
NOP 2
a + 2
T4
7
DI
101
a + 3
DI
NOP 2
T5
DI
b
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7
b + 1
DI
NOP 2
b + 2
T6
DI
1Gb: x4, x8, x16 DDR2 SDRAM
7
b + 3
DI
Valid 4
b + 4
T7
DI
t
7
t
DQSS.
CK from previous WRITE.
Transitioning Data
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b + 5
DI
Valid 4
b + 6
T8
DI
7
t
WR where
Operations
b + 7
DI
Valid 4
T9
Don’t Care
t
WR