mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 83

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Off-Chip Driver (OCD) Impedance Calibration
Posted CAS Additive Latency (AL)
Figure 41:
PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
DQS, DQS#
Command
CK#
DQ
CK
ACTIVE n
T0
READ Latency
Notes:
READ n
T1
ODT must be turned off prior to entering self refresh mode. During power-up and initial-
ization of the DDR2 SDRAM, ODT should be disabled until the EMR command is issued.
This will enable the ODT feature, at which point the ODT ball will determine the R
(EFF) value. Anytime the EMR enables the ODT function, ODT may not be driven HIGH
until eight clocks after the EMR has been enabled (see Figure 82 on page 121 for ODT
timing diagrams).
The OFF-CHIP DRIVER function is an optional DDR2 JEDEC feature not supported by
Micron and thereby must be set to the default state. Enabling OCD beyond the default
settings will alter the I/O drive characteristics and the timing and output I/O specifica-
tions will no longer be valid (see "Initialization" on page 73 for proper setting of OCD
defaults).
Posted CAS additive latency (AL) is supported to make the command and data bus effi-
cient for sustainable bandwidths in DDR2 SDRAM. Bits E3–E5 define the value of AL, as
shown in Figure 40 on page 81. Bits E3–E5 allow the user to program the DDR2 SDRAM
with an AL of 0, 1, 2, 3, 4, 5, or 6 clocks. Reserved states should not be used as an
unknown operation or incompatibility with future versions may result.
In this operation, the DDR2 SDRAM allows a READ or WRITE command to be issued
prior to
using this feature would set AL =
held for the time of the AL before it is issued internally to the DDR2 SDRAM device. RL is
controlled by the sum of AL and CL; RL = AL + CL. Write latency (WL) is equal to RL
minus one clock; WL = AL + CL - 1 ×
page 83. An example of a WL is shown in Figure 42 on page 84.
1. BL = 4.
2. Shown with nominal
3. RL = AL + CL = 5.
t RCD (MIN)
AL = 2
t
NOP
RCD (MIN) with the requirement that AL ≤
T2
NOP
T3
t
AC,
RL = 5
t
DQSCK, and
83
NOP
t
T4
RCD (MIN) - 1 ×
t
CK. An example of RL is shown in Figure 41 on
CL = 3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
DQSQ.
NOP
T5
1Gb: x4, x8, x16 DDR2 SDRAM
t
CK. The READ or WRITE command is
t
RCD (MIN). A typical application
NOP
T6
DO
n
Transitioning Data
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n + 1
DO
NOP
T7
n + 2
DO
Operations
n + 3
DO
Don’t Care
NOP
T8
TT